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b) Complete the excitation table (Table 2) for the counter and obtain logic expression for the JK flip-flop input functions. Table 2. Next state Flip-flop input functions JB KB Present state A В A В JА KA 1 1 1 1 Flip-flop input functions are: JA= KA= JB= KB=

b) Complete the excitation table (Table 2) for the counter and obtain logic expression for the JK flip-flop input functions. Table 2. Next state Flip-flop input functions JB KB Present state A В A В JА KA 1 1 1 1 Flip-flop input functions are: JA= KA= JB= KB=

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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3. A Synchronous Counters Asynchronous counters are a series of flip-flops each clocked by the previous state, one after the other. Since all the stages of the counter are not clocked together, a ripple effect propagates as various flip-flops are clocked. For this reason they are called ripple counters. The modulus of a counter is the number of different output states the counter may take (i.e. Mod 4 means the counter has four output states). a) In the pre-lab construct a 4-bit asynchronous counter shown in Fig.3. (It is also called binary ripple counter). Use four generic JK flip-flops. Connect four Binary Probes to Q outputs. Connect all R and S inputs to Logic 1 and connect a switch to the CP input. J J J J ср Q Q Q Fig. 3 4-bit ripple counter b) In the Lab use two 7476 ICs to implement the design. Connect Q outputs of flip-flops to indicator lamps of the PB-503. Connect all clear (CLR) and preset (PRE) inputs to logic 1. Connect the CP input to the pulse output of the PB-503 and check the counter for proper operation.
Transcribed Image Text:3. A Synchronous Counters Asynchronous counters are a series of flip-flops each clocked by the previous state, one after the other. Since all the stages of the counter are not clocked together, a ripple effect propagates as various flip-flops are clocked. For this reason they are called ripple counters. The modulus of a counter is the number of different output states the counter may take (i.e. Mod 4 means the counter has four output states). a) In the pre-lab construct a 4-bit asynchronous counter shown in Fig.3. (It is also called binary ripple counter). Use four generic JK flip-flops. Connect four Binary Probes to Q outputs. Connect all R and S inputs to Logic 1 and connect a switch to the CP input. J J J J ср Q Q Q Fig. 3 4-bit ripple counter b) In the Lab use two 7476 ICs to implement the design. Connect Q outputs of flip-flops to indicator lamps of the PB-503. Connect all clear (CLR) and preset (PRE) inputs to logic 1. Connect the CP input to the pulse output of the PB-503 and check the counter for proper operation.
b) Complete the excitation table (Table 2) for the counter and obtain logic expression for the JK flip-flop input functions. Table 2. Present state Next state Flip-flop input functions А В A JA КА JB KB 1 1 1 1 Flip-flop input functions are: JA= ΚΑ- JB= KB= c) In the lab, build the circuit and test it by pulsing it from the PB-503. Check that the output is the designed sequence
Transcribed Image Text:b) Complete the excitation table (Table 2) for the counter and obtain logic expression for the JK flip-flop input functions. Table 2. Present state Next state Flip-flop input functions А В A JA КА JB KB 1 1 1 1 Flip-flop input functions are: JA= ΚΑ- JB= KB= c) In the lab, build the circuit and test it by pulsing it from the PB-503. Check that the output is the designed sequence
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