Computer Organization/Design question (RISC-V) Assume that the following RISC-V code is executed on a pipelined processor with a 5-stagepipeline with full forwarding and a predict-taken branch predictor. Draw the pipeline diagramand report number of clock cycles it takes to execute this sequence of instructions.Note: Result of branch is determined in EXE stage.Labell:Label2:1wbeq x2add X1beq X1SW X2and X1X1, 40 (X6)X3""""IX6X2ILabel2X4Label1I20 (X4)X1 X4* Please solve correctly. Thank you.#Not Taken#Not Taken

In pipelined processors, instruction execution is divided into stages (e.g., IF, ID, EXE, MEM, WB).Each stage processes a different aspect of an instruction simultaneously. Forwarding facilitates to resolve data data hazards by passing data directly between stages. In branch prediction, the outcome is predicted to reduce pipeline stalls.Here, the given RISC-V code undergoes a 5-stage pipeline, utilizing full forwarding and a predict-taken branch predictor, taking advantage of parallel processing for improved performance.IF: Instruction FetchID: Instruction DecodeEXE: ExecuteMEM: Memory AccessWB: Write Back Cycle 1:lw X1, 40 (X6): IFIDEXEMEMWBlwFirst instruction will go to Instruction fetch step.Cycle 2:beq X2, X3, Label2:Branch is not taken, so no pipeline flush. IFIDEXEMEMWBbeqlwCycle 3: add X1, X6, X4: Previous instruction (beq) did not flush the pipeline. IFIDEXEMEMWBaddbeqlwCycle 4: beg X1, X2, Label1: Branch is not taken, so no pipeline flush. IFIDEXEMEMWBbegaddbeqlwCycle 5: SW X2, 20 (X4): Previous instruction (beg) did not flush the pipeline. IFIDEXEMEMWBswbegadd beqlwCycle 6: and X1, X1, X4: Here, the last instruction goes to the IF state while first instruction lw completes the entire pipeline.IFIDEXEMEMWBandswbegaddbeqHence, as we can observe it takes 6 clock cycles to execute this sequence of instructions.