Assume that the following are concurrent VHDL statements: (a) L <= P nand Q after 10 ns; (b) M <= L nor N after 5 ns; (c) R <= not M; Initially at time t = 0 ns, P = 1, Q = 1, and N = 0. If Q becomes 0 at time t = 4 ns, (1) At what time will statement (a) execute? (2) At what time will L be updated? (3) At what time will statement (c) execute? (4) At what time will R be updated?

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Assume that the following are concurrent VHDL statements:

(a) L <= P nand after 10 ns;

(b) M <= L nor after 5 ns;

(c) R <= not M;

Initially at time = 0 ns, P = 1, Q = 1, and N = 0. If Q becomes 0 at time = 4 ns,

(1) At what time will statement (a) execute?

(2) At what time will L be updated?

(3) At what time will statement (c) execute?

(4) At what time will R be updated?

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