Assume register R1 contains an arbitrary integer A, and R2 contains an arbitrary integer B. Which of the following sequences of machine instructions implement the exact condition A < B so that the branch skips the halt instruction? Mark all correct choices. FYI: Be certain; Canvas deducts points for incorrect choices. 0 U U 1001 011 001 1 11111 0001 011 011 1 00001 0001 011 010 0 00 011 0000 001 000011111 1111 0000 0010 0101 0001 011 001 0 00 010 0000 001 000011111 1111 0000 0010 0101 1001 011 001 1 11111 0001 011 011 1 00001 0001 011 010 0 00 011 0000 101 000011111 1111 0000 0010 0101 1001 011 010 1 11111 0001 011 011 1 00001 0001 011 001 0 00 011 0000 010 000011111 1111 0000 0010 0101 1001 011 010 1 11111 0001 011 011 1 00001 0001 011 001 0 00 011 0000 100 000011111 1111 0000 0010 0101 0001 011 001 0 00 010 0000 101 000011111 1111 0000 0010 0101
Assume register R1 contains an arbitrary integer A, and R2 contains an arbitrary integer B. Which of the following sequences of machine instructions implement the exact condition A < B so that the branch skips the halt instruction? Mark all correct choices. FYI: Be certain; Canvas deducts points for incorrect choices. 0 U U 1001 011 001 1 11111 0001 011 011 1 00001 0001 011 010 0 00 011 0000 001 000011111 1111 0000 0010 0101 0001 011 001 0 00 010 0000 001 000011111 1111 0000 0010 0101 1001 011 001 1 11111 0001 011 011 1 00001 0001 011 010 0 00 011 0000 101 000011111 1111 0000 0010 0101 1001 011 010 1 11111 0001 011 011 1 00001 0001 011 001 0 00 011 0000 010 000011111 1111 0000 0010 0101 1001 011 010 1 11111 0001 011 011 1 00001 0001 011 001 0 00 011 0000 100 000011111 1111 0000 0010 0101 0001 011 001 0 00 010 0000 101 000011111 1111 0000 0010 0101
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
Related questions
Question
Please choose ALL (multiple answers) correct answers) with explanation. Thank you!
![Assume register R1 contains an arbitrary integer A, and R2 contains an arbitrary integer B.
Which of the following sequences of machine instructions implement the exact condition A
< B so that the branch skips the halt instruction?
Mark all correct choices. FYI: Be certain; Canvas deducts points for incorrect choices.
1001 011 001 1 11111
0001 011 011 1 00001
0001 011 010 0 00 011
0000 001 000011111
1111 0000 0010 0101
0001 011 001 0 00 010
0000 001 000011111
1111 0000 0010 0101
1001 011 001 1 11111
0001 011 011 1 00001
0001 011 010 0 00 011
0000 101 000011111
1111 0000 0010 0101
1001 011 010 1 11111
0001 011 011 1 00001
0001 011 001 0 00 011
0000 010 000011111
1111 0000 0010 0101
1001 011 010 1 11111
0001 011 011 1 00001
0001 011 001 00 011
0000 100 000011111
1111 0000 0010 0101
0001 011 001 0 00 010
0000 101 000011111
1111 0000 0010 0101](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F582ddd12-f1f2-413d-867c-2f61c510c057%2F1ea41978-fd81-4eb6-afc3-1ca48de68641%2Fg3xj5v_processed.jpeg&w=3840&q=75)
Transcribed Image Text:Assume register R1 contains an arbitrary integer A, and R2 contains an arbitrary integer B.
Which of the following sequences of machine instructions implement the exact condition A
< B so that the branch skips the halt instruction?
Mark all correct choices. FYI: Be certain; Canvas deducts points for incorrect choices.
1001 011 001 1 11111
0001 011 011 1 00001
0001 011 010 0 00 011
0000 001 000011111
1111 0000 0010 0101
0001 011 001 0 00 010
0000 001 000011111
1111 0000 0010 0101
1001 011 001 1 11111
0001 011 011 1 00001
0001 011 010 0 00 011
0000 101 000011111
1111 0000 0010 0101
1001 011 010 1 11111
0001 011 011 1 00001
0001 011 001 0 00 011
0000 010 000011111
1111 0000 0010 0101
1001 011 010 1 11111
0001 011 011 1 00001
0001 011 001 00 011
0000 100 000011111
1111 0000 0010 0101
0001 011 001 0 00 010
0000 101 000011111
1111 0000 0010 0101
![Table of LC-3 Instructions:
NOT
ADD
AND
ADD
AND
LDR
STR
LD
ST
LDI
STI
LEA
BR
JMP
TRAP
15 14 13 12 11 10 9 8 7 6 5 4 3210
1
O
1 DST
SRC
1 1
1
DST
SRC1
0 0
1
DST
SRC1
000
1
DST
SRC 1
1
DST
SRC
1
1 1 O
DST
BASE
O 1 1 1
SRC
BASE
1 O
DST
1 1
SRC
1
1 O
DST
1
1 1
SRC
1 1 1 O
DST
O
O
1 O
O
O
O 1
O
O
O
O
O
ο ο ο ο Ν ΖΡ
UNUSED 1 1 01
1 1
00
1 1 1 10
BASE
000
1 1 1
Immediate (5)
Immediate (5)
Offset (6)
Offset (6)
PC Offset (9)
PC Offset (9)
PC Offset (9)
PC Offset (9)
PC Offset (9)
SRC2
SRC2
PC Offset (9)
are set by ADD, AND, NOT, LD, LDR, LDI, LEA
are used by BR based on the most recent instruction to set CC
4. Trap Vector is an 8-bit value that is used to call an OS service routine:
o Ox21 output a character
o
Ox23 input a character
o Ox25 halt the program
1
0 0 0 0 0 0
Trap Vector (8)
SEMANTICS
R[DST] NOT(R[SRC])
R[DST] R[SRC1] + R[SRC2]
R[DST]
R[SRC1] & R[SRC2]
R[DST]
R[SRC] + SEXT(Immediate5)
R[DST] R[SRC] & SEXT(Immediate5)
R[DST] M[R[BASE]+SEXT(Offset6)]
M[R[BASE]+SEXT(Offset6)] ← R[SRC]
R[DST] M[inc(PC)+SEXT(PCOffset9)]
M[inc(PC)+SEXT(PCOffset9)] ← R[SRC]
R[DST] M[M[inc(PC)+SEXT(PCOffset9)]]
Notes:
1. BASE, SRC, SRC1, SRC2, DST are 3-bit register designations that access the Register File, R[...]
2. Immediate, Offset, PC Offset are N-bit 2's complement integers, where N is given in ()'s above
3. Condition Codes
M[M[inc(PC)+SEXT(PCOffset9)]] ← R[SRC]
R[DST] inc(PC)+SEXT(PCOffset9)
PC inc(PC)+SEXT(PCOffset9) if condition set
else PC inc(PC) See Note 3 below.
PC ← R[BASE]
jump to trap vector, See Note 4 below.
invalid instruction](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F582ddd12-f1f2-413d-867c-2f61c510c057%2F1ea41978-fd81-4eb6-afc3-1ca48de68641%2Fakdc8wn_processed.jpeg&w=3840&q=75)
Transcribed Image Text:Table of LC-3 Instructions:
NOT
ADD
AND
ADD
AND
LDR
STR
LD
ST
LDI
STI
LEA
BR
JMP
TRAP
15 14 13 12 11 10 9 8 7 6 5 4 3210
1
O
1 DST
SRC
1 1
1
DST
SRC1
0 0
1
DST
SRC1
000
1
DST
SRC 1
1
DST
SRC
1
1 1 O
DST
BASE
O 1 1 1
SRC
BASE
1 O
DST
1 1
SRC
1
1 O
DST
1
1 1
SRC
1 1 1 O
DST
O
O
1 O
O
O
O 1
O
O
O
O
O
ο ο ο ο Ν ΖΡ
UNUSED 1 1 01
1 1
00
1 1 1 10
BASE
000
1 1 1
Immediate (5)
Immediate (5)
Offset (6)
Offset (6)
PC Offset (9)
PC Offset (9)
PC Offset (9)
PC Offset (9)
PC Offset (9)
SRC2
SRC2
PC Offset (9)
are set by ADD, AND, NOT, LD, LDR, LDI, LEA
are used by BR based on the most recent instruction to set CC
4. Trap Vector is an 8-bit value that is used to call an OS service routine:
o Ox21 output a character
o
Ox23 input a character
o Ox25 halt the program
1
0 0 0 0 0 0
Trap Vector (8)
SEMANTICS
R[DST] NOT(R[SRC])
R[DST] R[SRC1] + R[SRC2]
R[DST]
R[SRC1] & R[SRC2]
R[DST]
R[SRC] + SEXT(Immediate5)
R[DST] R[SRC] & SEXT(Immediate5)
R[DST] M[R[BASE]+SEXT(Offset6)]
M[R[BASE]+SEXT(Offset6)] ← R[SRC]
R[DST] M[inc(PC)+SEXT(PCOffset9)]
M[inc(PC)+SEXT(PCOffset9)] ← R[SRC]
R[DST] M[M[inc(PC)+SEXT(PCOffset9)]]
Notes:
1. BASE, SRC, SRC1, SRC2, DST are 3-bit register designations that access the Register File, R[...]
2. Immediate, Offset, PC Offset are N-bit 2's complement integers, where N is given in ()'s above
3. Condition Codes
M[M[inc(PC)+SEXT(PCOffset9)]] ← R[SRC]
R[DST] inc(PC)+SEXT(PCOffset9)
PC inc(PC)+SEXT(PCOffset9) if condition set
else PC inc(PC) See Note 3 below.
PC ← R[BASE]
jump to trap vector, See Note 4 below.
invalid instruction
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Here, you answered when A = B. But the question asks when A < B. I was wondering if you could please re-phase so when A < B. Thank you!
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