and ID stage is divid nd ID2) with equal inex and y memory r overlapped so the p instructions in the n the pipeline 'y i a

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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Consider a pipeline 'x' consist of 5 stages named
as IF, ID, OF, EX and WB with the respective
stage delays of 2 ns, 5 ns, 6 ns, 8 ns and 1 ns.
The alternative pipeline 'y' contain the same
number of stages but EX stage is divided into 4
sub stages, (EX1, EX2, EX3 and EX4) with equal
delay i.e. (8 ns/4) and ID stage is divided into 2
substages (ID1 and ID2) with equal delays of
(5 ns/2). In the pipelinex and y memory reference
instructions are not overlapped so the penalty of
memory reference instructions in the pipeline
'x'is 4 cycles and in the pipeline 'y is 8 cycles.
If the program contain 30% of the instructions
which are memory based instructions, what is
the ratio of speedup of x to speedup of y?
Transcribed Image Text:Consider a pipeline 'x' consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 5 ns, 6 ns, 8 ns and 1 ns. The alternative pipeline 'y' contain the same number of stages but EX stage is divided into 4 sub stages, (EX1, EX2, EX3 and EX4) with equal delay i.e. (8 ns/4) and ID stage is divided into 2 substages (ID1 and ID2) with equal delays of (5 ns/2). In the pipelinex and y memory reference instructions are not overlapped so the penalty of memory reference instructions in the pipeline 'x'is 4 cycles and in the pipeline 'y is 8 cycles. If the program contain 30% of the instructions which are memory based instructions, what is the ratio of speedup of x to speedup of y?
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