Analyse Verilog code in Figure 1 and modify the code to fulfil the following conditions:a) Add two more states: state C with state code 10, and state D with state code 11.b) State C will transit to state D if input X is 0 (output Z is 0), but it will remain in stateC if input X is 1 (output Z is 0).c) State D will transit to state A if input X is 0 (output Z is 0), and it will transit to stateB if input X is 1 (output Z is 1). 2. Simulate the modified code by using input values shown in Figure 2. Verify yourwaveform by referring to the outputs in the figure.40.0 ns80.0 ns120,0 ns160,0 ns200,0 ns240.0 nsps280.0 ns320.0 nsNameO psCLKRESETinut> present_state00010001101101000110aut> next_state00010001101101000100011011outFigure 23. Next, record a short video (3-5 minutes) to explain all the steps involved in getting correctwaveform for the modified code. The steps should start with Open Project and ends withcorrect simulated waveform. Please also explain your observation on the output waveform.4. Lastly, write a report to discuss modifications that you have performed to the Verilog codein Figure 1 and your findings from the simulated waveform. Therefore, your report mustinclude all the following:a) Verilog code that has been modified.b) State diagram of the Verilog code.c) State table of the Verilog code.d) Discussion on the type of FSM machine used for the Verilog code, and your resultsobtained from the simulated waveform. Please include your simulated waveform inthe report.e) Detail discussion on your observation for time frame 230.0ns until 310.0ns in Figure2.5. Please submit your report in PDF and save as the file using the following file name format:FullName_MatricNumber.pdf Emodule state_machine (CLK, RESET, X, z,L1present_state, next_state);3input CLK, RESET, X;4output z;output present_state, next_state;6.reg present_state, next_state;parameter A = l'b0, B = l'bl;78.reg 2;always @ (posedge CLK or posedge RESET)Abeginif (RESET)10111213present_state <= A;14else15present_state <= next_state;16end17always e (X or present_state)Abegin1819case (present_state)A: next state = X ? B : A;B: next_state = X ? A : C;20212223endcase24end25always e (X or present_state)Abegin2627case (present state)A: z = 1'b0;B: z - 1'b0;28293031endcase32end33endmoduleFigure 1

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Answered: Analyse Verilog code in Figure 1 and…

Computer Networking: A Top-Down Approach (7th Edition)

7th Edition

ISBN:9780133594140

Author:James Kurose, Keith Ross

Publisher:James Kurose, Keith Ross

Chapter1: Computer Networks And The Internet

Section: Chapter Questions

Problem R1RQ: What is the difference between a host and an end system? List several different types of end...

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Analyse Verilog code in Figure 1 and modify the code to fulfil the following conditions:
a) Add two more states: state C with state code 10, and state D with state code 11.
b) State C will transit to state D if input X is 0 (output Z is 0), but it will remain in state
C if input X is 1 (output Z is 0).
c) State D will transit to state A if input X is 0 (output Z is 0), and it will transit to state
B if input X is 1 (output Z is 1).