An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies 1ns, 2.2ns, 2ns, 1ns, and 0.75ns, respectively (ns stands for nanosecor ds). To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. Also, the EX stage is split into two stages (EX1, EX2) each of latency 1ns. The new design has a total of eight pipeline stages. A program has 20% branch instructions which execute in the EX stage and produce the next instruction pointer at the end of the EX stage in the old design and at the end of the EX2 stage in the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average CPI of one in both the designs. The execution times of this program on the old and the new design are P and Q nanoseconds, respectively. The value of PIQ is
An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies 1ns, 2.2ns, 2ns, 1ns, and 0.75ns, respectively (ns stands for nanosecor ds). To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. Also, the EX stage is split into two stages (EX1, EX2) each of latency 1ns. The new design has a total of eight pipeline stages. A program has 20% branch instructions which execute in the EX stage and produce the next instruction pointer at the end of the EX stage in the old design and at the end of the EX2 stage in the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average CPI of one in both the designs. The execution times of this program on the old and the new design are P and Q nanoseconds, respectively. The value of PIQ is
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Transcribed Image Text:An instruction pipeline has five stages, namely,
instruction fetch (IF), instruction decode and
register fetch (ID/RF), instruction execution (EX),
memory access (MEM), and register writeback
(WB) with stage latencies 1ns, 2.2ns, 2ns, 1ns,
and 0.75ns, respectively (ns stands for
nanosecords). To gain in terms of frequency, the
designers have decided to split the ID/RF stage
into three stages (ID, RF1, RF2) each of latency
2.2/3 ns. Also, the EX stage is split into two stages
(EX1, EX2) each of latency lns. The new design
has a total of eight pipeline stages. A program
has 20% branch instructions which execute in
the EX stage and produce the next instruction
pointer at the end of the EX stage in the old design
and at the end of the EX2 stage in the new design.
The IF stage stalls after fetching a branch
instruction until the next instruction pointer is
computed. All instructions other than the branch
instruction have an average CPI of one in both
the designs. The execution times of this program
on the old and the new design are P and Q
nanoseconds, respectively. The value of PIQ is
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