Add Izero 4-> (O MOX- (0 ALU Add, 1 result Shift RegDst Branch left 2 MemRead Instruction [31-26] MemtoReg Control ALUOP MemWrite ALUSrc PCSrce RegWrite Instruction [25-21] Read PC Read address register 1 Read Instruction [20-16] data 1 Read Zero Instruction [31-0] register 2 M Write Read data 2 ALU ALU Read Ο Instruction Instruction [15-11] register memory Write data Registers OMIX) Address result data M Write Data data memory Instruction [15-0] 16 32 Sign- extend ALU control Instruction [5-0]

Programming Logic & Design Comprehensive
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Author:FARRELL
Publisher:FARRELL
Chapter3: Understanding Structure
Section: Chapter Questions
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li   $t2, 2

L1:

add   $t1, $t1, $t2

 

sub   $t1, $t1, $t3

 

bne   $t1, $t4, L1

 

sub   $t4, $s0, $t3


Given the modified single-cycle processor shown below, what are the values (in binary) of instruction[31-26], instruction[25-21], instruction[20-16], instruction[15-11], instruction[5-0], Read data 1, Read data 2, ALU zero, PCSrc, and all the main control decoded output signals when the time is at 1950 ns. The below single-cycle processor diagram can be used for your reference.

Note: A new decoded signal output “Tzero” is added for executing “bne” instruction. The signal definition is described below:

Instruction

Opcode

New Main Control Output Signal

beq

00100b (4d)

Tzero = 0

bne

00101b (5d)

Tzero = 1

 

At the moment of 1950 ns, the below values (0, 1 or X) are:
instruction[31-26] = 
instruction[25-21] = 
instruction[20-16] =
instruction[15-0] = 

Read data 1 output = 

Read data 2 output = 

RegDst = 

ALUSrc = 

MemtoReg = 

RegWrite = 

MemRead = 

MemWrite = 

Branch = 

ALUop[1:0] = 

ALU zero = 

PCSrc = 

Add
Izero
4->
(O MOX-
(0
ALU
Add,
1
result
Shift
RegDst
Branch
left 2
MemRead
Instruction [31-26]
MemtoReg
Control
ALUOP
MemWrite
ALUSrc
PCSrce
RegWrite
Instruction [25-21]
Read
PC
Read
address
register 1 Read
Instruction [20-16]
data 1
Read
Zero
Instruction
[31-0]
register 2
M
Write
Read
data 2
ALU ALU
Read
Ο
Instruction
Instruction [15-11]
register
memory
Write
data Registers
OMIX)
Address
result
data
M
Write
Data
data memory
Instruction [15-0]
16
32
Sign-
extend
ALU
control
Instruction [5-0]
Transcribed Image Text:Add Izero 4-> (O MOX- (0 ALU Add, 1 result Shift RegDst Branch left 2 MemRead Instruction [31-26] MemtoReg Control ALUOP MemWrite ALUSrc PCSrce RegWrite Instruction [25-21] Read PC Read address register 1 Read Instruction [20-16] data 1 Read Zero Instruction [31-0] register 2 M Write Read data 2 ALU ALU Read Ο Instruction Instruction [15-11] register memory Write data Registers OMIX) Address result data M Write Data data memory Instruction [15-0] 16 32 Sign- extend ALU control Instruction [5-0]
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