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a. What is the cache block size (in words)? b. How many entries does the cache have? c. What is the ratio between total bits required for such a cache implementation over the da storage bits?

a. What is the cache block size (in words)? b. How many entries does the cache have? c. What is the ratio between total bits required for such a cache implementation over the da storage bits?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question 3: For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 Offset 4-0 a. What is the cache block size (in words)? b. How many entries does the cache have? c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
Transcribed Image Text:Question 3: For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-10 Index 9-5 Offset 4-0 a. What is the cache block size (in words)? b. How many entries does the cache have? c. What is the ratio between total bits required for such a cache implementation over the data storage bits?
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