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A typical digital signal processing (DSP) system is given in figure below. ADC has 100MHZ sampling clock and every samples will be captured by FPGA for backend processing. An interpolator increases the sampling rate by a factor of 4 to generate the sample stream of y(n). Then, a decimation block will reduce the sampling rate by a factor of 15 to generate sample stream of z(n). 100MHZ FPGA z(n) Decimator x(t) x(n) y(n) ADC Interpolator LPF1 LPF2 i. When LPF1 (Low Pass Filter 1) and LPF2 are implemented using a 30-taps FIR structure, and the system must operate in streaming way (every samples must be processed without any halt), what will be required FPGA clock frequency and what type of FIR filter structures should be used? Input samples are 12-bits and coefficients are 10-bits for both filters. Determine the number and the size of multiplication and addition operations in FPGA to implement LPF1 and LPF2. Comment on the bit growth and what kind of digital operations should be implemented before LPF2 to reduce the hardware cost?

A typical digital signal processing (DSP) system is given in figure below. ADC has 100MHZ sampling clock and every samples will be captured by FPGA for backend processing. An interpolator increases the sampling rate by a factor of 4 to generate the sample stream of y(n). Then, a decimation block will reduce the sampling rate by a factor of 15 to generate sample stream of z(n). 100MHZ FPGA z(n) Decimator x(t) x(n) y(n) ADC Interpolator LPF1 LPF2 i. When LPF1 (Low Pass Filter 1) and LPF2 are implemented using a 30-taps FIR structure, and the system must operate in streaming way (every samples must be processed without any halt), what will be required FPGA clock frequency and what type of FIR filter structures should be used? Input samples are 12-bits and coefficients are 10-bits for both filters. Determine the number and the size of multiplication and addition operations in FPGA to implement LPF1 and LPF2. Comment on the bit growth and what kind of digital operations should be implemented before LPF2 to reduce the hardware cost?

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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A typical digital signal processing (DSP) system is given in figure below. ADC has 100MHZ sampling clock and every samples will be captured by FPGA for backend processing. An interpolator increases the sampling rate by a factor of 4 to generate the sample stream of y(n). Then, a decimation block will reduce the sampling rate by a factor of 15 to generate sample stream of z(n). 100MHZ FPGA z(n) Decimator x(t) х(п) y(n) ADC Interpolator LPF1 LPF2 i. When LPF1 (Low Pass Filter 1) and LPF2 are implemented using a 30-taps FIR structure, and the system must operate in streaming way (every samples must be processed without any halt), what will be required FPGA clock frequency and what type of FIR filter structures should be used? Input samples are 12-bits and coefficients are 10-bits for both filters. Determine the number and the size of multiplication and addition operations in FPGA to implement LPF1 and LPF2. Comment on the bit growth and what kind of digital operations should be implemented before LPF2 to reduce the hardware cost?
Transcribed Image Text:A typical digital signal processing (DSP) system is given in figure below. ADC has 100MHZ sampling clock and every samples will be captured by FPGA for backend processing. An interpolator increases the sampling rate by a factor of 4 to generate the sample stream of y(n). Then, a decimation block will reduce the sampling rate by a factor of 15 to generate sample stream of z(n). 100MHZ FPGA z(n) Decimator x(t) х(п) y(n) ADC Interpolator LPF1 LPF2 i. When LPF1 (Low Pass Filter 1) and LPF2 are implemented using a 30-taps FIR structure, and the system must operate in streaming way (every samples must be processed without any halt), what will be required FPGA clock frequency and what type of FIR filter structures should be used? Input samples are 12-bits and coefficients are 10-bits for both filters. Determine the number and the size of multiplication and addition operations in FPGA to implement LPF1 and LPF2. Comment on the bit growth and what kind of digital operations should be implemented before LPF2 to reduce the hardware cost?
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