[A] Suppose that a 16M x 32 main memory is built using 512K x 16 RAM chips and that the memory is word addressable. a- How many RAM chips are necessary to build the 16M x 32 main memory? b- If we were accessing one full work, how many chips would be involved? C- How many address bits are need for each RAM chip? d- How may memory banks will this memory have? How many address bits are needed for all memory? е-

[A] Suppose that a 16M x 32 main memory is built using 512K x 16 RAM chips and that the memory is word addressable. a- How many RAM chips are necessary to build the 16M x 32 main memory? b- If we were accessing one full work, how many chips would be involved? C- How many address bits are need for each RAM chip? d- How may memory banks will this memory have? How many address bits are needed for all memory? е-

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Related questions

Q: For a 512k x 32 memory system, how wide does the incoming address bus needed to be in order to…

A: Given, Size of memory system = 512k x 32 For a p x q memory system, Size of address bus = log 2 p…

Q: Show work and type answer please. Suppose a computer using fully associate cache has 2G Bytes of…

A: In this question, we are given a fully associative cache with main memory and block size. We are…

Q: In the MC68000 microprocessor, the total memory address is 16 MB and it is based on address pins. i.…

A: Answer: I have given answer in the brief explanation.

Q: ing questions:

A: An integrated circuit made out of millions of capacitors and transistors that can store data or can…

Q: a) How many bits does a processor need internally to address a 32M x 32 memory if the memory is word…

A: As per Bartleby guideline we can only provide only 3 subparts.

Q: Suppose memory holds the following data values in these addresses: Address: Data: 1000: 25 1004: 33…

A: This is has used the concept of index addressing mode. Here is the explanation:

Q: Design a memory system for the 8088 Microprocessor such that it can select two EPROMS (128K x 8)…

Q: A byte-addressable computer uses 32-bit address to access main memory. Suppose the data cache…

A: To determine the number of bits in the tag, index, and offset, as well as the total cache size, we…

Q: (b) The following memory units are specified by the number of words times the number of bits per…

Q: Question 1: For a RAM memory of size 256K x 16, answer the following? a) How many address lines are…

A: INTRODUCTION: The CPU's data is now being used in the computer's short-term memory, which is…

Q: Answer any 2 or 3 question among all

A: A virtual address space or address space is the set of ranges of virtual addresses that an operating…

Q: 12-5. A computer employs RAM chips of 256 × 8 and ROM chips of 1024 × 8. The computer system needs…

A: In this question we have given some information related to size of memory components and we need to…

Q: 2. Design your own 16 bits Memory Map, and choose the amount of memory space required for various…

A: 16bit processor,16bit(word-sized), can address 64k of RAM. 220(1048576)bytes, so can construct 20bit…

Q: Suppose we have a 64Kbyte byte-addressable memory that is 16-way low-order interleaved. What is the…

A: In a 16KB memory, we have 214 bytes (since 1KB = 210 bytes). The memory is 16-way low-order…

Q: We want to build a byte organized main memory of 8 GB for a 32-bit CPU architecture composed of byte…

A: In computer architecture, which it is the 32-bit CPU that refers to a processor that can process…

Q: SUBJECT: COMPUTER ORGANASATION 1. a. How many address bits are required to access 256K words of…

Q: (d) A process wishes to transfer to main memory n bytes of data from an I/O device which can…

A: Answer is given answer-

Q: Suppose we have the instr Memory 100 600 R1| ... 400 300 ... 500 100 600 500 ... 700 800 Assume R1…

A: It is defined as the ways how architectures specify the address of an object they want to access. In…

Q: For a 512k x 32 memory system, how wide does the incoming address bus needed to be in order to…

A: Here is the explanation about the width of the address bus:

Q: ss bus and multiple blocks of 1MB memory units. It is ory system that maximizes the main memory size…

A: Answer is in given below:-

Q: A computer system employed memory-mapped 1/0 with 16-bit address bus to access its memory and the…

A: A computer employs RAM chips of 256 x 8 ROM chips of 1024x8.

Q: In a semiconductor ROM memory organized using 2-Dimensional addressing, the number of NMOS NOR gates…

A: Option c is correct Correct answer : c. 2^( The number of row address bits).

Q: 1. a. How many bits are required to address a 32M x 32 memory if: Main memory is byte addressable?…

A: Byte and word: 1 byte = 8 bits. 1 word = 2 bytes = 2 x 8 = 16 bits.

Q: 1. Write about the entire details of memory structure design and characteristics. 2. How much the…

A: answer is given below:-

Q: CPU Main Memory Instructions Space MAR ALU MBR АС BUS PC Control Data Space Cache Explain in your…

A: Here it is the architecture of the simple processor, it having the two main blocks those are CPU and…

Q: Consider a processor with a 16-entry TLB that uses 2 KB pages. What are the performance consequences…

A: The raw computational capacity of CPU centers is a significant segment of framework level execution,…

Q: What is the minimum size memory in byte that this computer system can have

A: (a)minimum size of memory = 1G x 8 bits = 1GBytes(b)maximum size of memory = 2^32 x 32 bits = 2^32 x…

Q: 1 The memory units that follow are specified by the number of words times the number of bits per…

A: Below is the answer to above question. I hope this will be helpful for you...

Q: Consider a memory of capacity 4MB. How many address lines do you think are needed to address all the…

A: Data within a computer system is accessed by means of metallic conductors known as address lines.…

Q: Figure illustrate the memory bank of a computer system. Same banks indicate the locations or address…

A: Dear student, As per guidelines, I can answer only first three subparts only. Please repost your…

Concept explainers

Fundamentals of Input and Output Performance

The I/O subsystem is a component of computer system design that uses buses to assist communication between the Central Processing Unit, Computer Memory/Storage, and Input and Output Devices (that is known as peripheral devices). The I/O subsystem includes disc controllers, tape drives, discs, system buses, and other devices. The I/O database application reads and writes drives using the operating system windows I/O.

Question

[A]
Suppose that a 16M x 32 main memory is built using 512K x 16 RAM chips and that the memory is word addressable.
a- How many RAM chips are necessary to build the 16M x 32 main memory?
b- If we were accessing one full work, how many chips would be involved?
How many address bits are need for each RAM chip?
C-
d- How may memory banks will this memory have?
e-
How many address bits are needed for all memory?

Expert Solution

This question has been solved!

Explore an expertly crafted, step-by-step solution for a thorough understanding of key concepts.

This is a popular solution!

SEE SOLUTION Check out a sample Q&A here

Step 1

Step 2

Step 3

Step 4

Step 5

Trending now

This is a popular solution!

Step by step

Solved in 5 steps

SEE SOLUTION Check out a sample Q&A here

Knowledge Booster

Fundamentals of Input and Output Performance

Learn more about

Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.

Similar questions

3. A computer has a cache memory with the following features: A. Size: 16KB with lines of 32 bytes (8 words) B. Access time: 10ns The cache memory is connected to a memory using a bus. The main memory transfers a block of 8 words in 120 ns. What is the hit ratio needed to obtain an average access time of 20 ns?
Suppose we have a 64Kbyte byte-addressable memory that is 16-way low-order interleaved. What is the size of the memory address module number field? Explain why.
Show work and give only correct answer
Suppose that a 16M X 16 memory built using 512K X 8 RAM chips and memory is word- addressable. You need to explain your answers with providing reasons or showing calculations. 1) How many RAM chips are necessary? 2) How many banks will this memory have? 3) How many address bits are needed for each RAM chip? 4) How many address bits are needed for all of memory? 5) If high-order interleaving is used, where would address 52 (base 10) be located? (What Bank# and what Offset#?)
8
Suppose that a 32M X 32 memory built using 512K X 8 RAM chips and memory is word-addressable. 1) How many RAM chips are necessary? 2) If we were accessing one full word, how many chips would be involved? 3) How many address bits are needed for each RAM chip? 4) How many banks will this memory have? 5f) If high-order interleaving is used, where would address 0x11011 be located? (Answer should be: bank# & offset#)
Given a computer with 300 memory locations, each 18-bit assessable, how many bits of addressing are needed? Given a computer with 10-bit addressability and 5 bits for the address, what's the maximum number of memory this computer can have in bits?
Please do a,b,c,d, and e Consider a machine with a byte addressable main memory of Bytes and block size of 8 Bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine. a.How is a 16-bit memory address divided into tag, line number, and byte number? b.Into what line would Bytes with of the following address be stored? 0001- 0001- 0001- 1011 1100- 0011- 0011- 0100 1101- 0000- 0001- 1101 1010- 1010- 1010- 1010 c.Suppose the byte with address 0001 1010 0001 1010 is stored in the cache. What are the addresses of the other bytes stored along with it? d.How many total bytes of memory can be stored in the cache? e.Why is the tag also stored in the cache?
Consider the following diagram and answer the following questions Is it SRAM or DRAM What is the size of this RAM How many input and output lines are there Explain working of all the components in this diagram.