A processor accesses main memory with an average access time of T2. A smaller cache memory is interposed between the processor and main memory. The cache has a significantly faster access time of T1 T2. The cache holds, at any time, copies of some main memory words and is designed so that the words more likely to be accessed in the near future are in the cache. Assume that the probability that the next word accessed by the processor is in the cache is H, known as the hit ratio. In practice, a system may be designed so that the processor must first access the cache to determine if the word is in the cache and, if it is not, then access main memory, so that on a miss (opposite of a hit), memory access time is T1 T2. Express T as a function of T1, T2, and H. Now calculate the speedup and compare to the result produced in the PREVIOUS part.
A processor accesses main memory with an average access time of T2. A smaller cache memory is interposed between the processor and main memory. The cache has a significantly faster access time of T1 T2. The cache holds, at any time, copies of some main memory words and is designed so that the words more likely to be accessed in the near future are in the cache. Assume that the probability that the next word accessed by the processor is in the cache is H, known as the hit ratio. In practice, a system may be designed so that the processor must first access the cache to determine if the word is in the cache and, if it is not, then access main memory, so that on a miss (opposite of a hit), memory access time is T1 T2. Express T as a function of T1, T2, and H. Now calculate the speedup and compare to the result produced in the PREVIOUS part.
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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A processor accesses main memory with an average access time of T2.
A smaller cache memory is interposed between the processor and main memory.
The cache has a significantly faster access time of T1 T2.
The cache holds, at any time, copies of some main memory words and is designed so that the words more likely to be accessed in the near future are in the cache.
Assume that the probability that the next word accessed by the processor is in the cache is H, known as the hit ratio.
- In practice, a system may be designed so that the processor must first access the cache to determine if the word is in the cache and, if it is not, then access main memory, so that on a miss (opposite of a hit), memory access time is T1 T2. Express T as a function of T1, T2, and H. Now calculate the speedup and compare to the result produced in the PREVIOUS part.
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