a- Explain the following code for a simple counter module simple_counter (clk, rst, count); input clk, rst; output [31:0] count; reg [31:0] count; always e (posedge clk) begin if (rst) count 32'b0; %3D else count = count + 1; %3D end endmodule b. modify the code in (a) so the counter supports asynchronous reset.

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Author:Robert L. Boylestad
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a- Explain the following code for a simple counter
module simple_counter (clk, rst, count);
input
clk, rst;
output [31:0] count;
reg [31:0]
count;
always e (posedge clk)
begin
if (rst)
count =
32'b0;
%3D
else
count = count + 1;
end
endmodule
b. modify the code in (a) so the counter supports asynchronous reset.
Transcribed Image Text:a- Explain the following code for a simple counter module simple_counter (clk, rst, count); input clk, rst; output [31:0] count; reg [31:0] count; always e (posedge clk) begin if (rst) count = 32'b0; %3D else count = count + 1; end endmodule b. modify the code in (a) so the counter supports asynchronous reset.
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