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A CPU can be viewed as a type of finite-state machine (FSM). i) The program counter is one example of CPU state. Identify two other types of state within a MIPS CPU.

A CPU can be viewed as a type of finite-state machine (FSM). i) The program counter is one example of CPU state. Identify two other types of state within a MIPS CPU.

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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2 CPUS are often implemented using FPGAS. FPGAS implement bit-wise logic in terms of k-LUTS (k input lookup-tables), which can implement any 1-bit function of k bits. Typically FPGAS use 4-LUTS, 5-LUTS, or 6-LUTS. Storage is implemented using 1-bit FFs (flip-flops). We will assume that the only thing that affects critical path is a LUT propagation delay of 1ns. A CPU can be viewed as a type of finite-state machine (FSM). a i) The program counter is one example of CPU state. Identify two other types of state within a MIPS CPU. ii) What are the inputs and outputs to a MIPS CPU when viewed as a state-machine? iii) Give a situation or scenario where the program-counter of a MIPS CPU is un-changed between two clock-cycles, but then changes on the following cycle. State any assumptions you make. iv) Assume that you have identified w; input bits, w, output bits, and ws state bits for a particular CPU. Given a hypothetical FPGA with unlimited k, so each LUT can have as many inputs as are needed, what is the minimum number of LUTS needed to implement the CPU? v) Assume that a single-cycle CPU is designed using 6-LUTS, and achieves a CPI of 10. If the CPU is then pipelined, what is the theoretical maximum IPC?
Transcribed Image Text:2 CPUS are often implemented using FPGAS. FPGAS implement bit-wise logic in terms of k-LUTS (k input lookup-tables), which can implement any 1-bit function of k bits. Typically FPGAS use 4-LUTS, 5-LUTS, or 6-LUTS. Storage is implemented using 1-bit FFs (flip-flops). We will assume that the only thing that affects critical path is a LUT propagation delay of 1ns. A CPU can be viewed as a type of finite-state machine (FSM). a i) The program counter is one example of CPU state. Identify two other types of state within a MIPS CPU. ii) What are the inputs and outputs to a MIPS CPU when viewed as a state-machine? iii) Give a situation or scenario where the program-counter of a MIPS CPU is un-changed between two clock-cycles, but then changes on the following cycle. State any assumptions you make. iv) Assume that you have identified w; input bits, w, output bits, and ws state bits for a particular CPU. Given a hypothetical FPGA with unlimited k, so each LUT can have as many inputs as are needed, what is the minimum number of LUTS needed to implement the CPU? v) Assume that a single-cycle CPU is designed using 6-LUTS, and achieves a CPI of 10. If the CPU is then pipelined, what is the theoretical maximum IPC?
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