A clocked Mealy sequential network has one input (X) and two outputs (Z1Z2).If Circuit receives (0,1,0) input while haven't received the (1,0,0) input before circuit would give Z1 = 1 result. For every (1,0,0) input received circuit would give Z2 = 1 output. If ever the circuit's Z2 output becomes Z2=1 circuit's Z1 output wont be Z1=1 afterwards but if Z1 output becomes Z1=1 it won't affect Z2 outputs capability of resulting 1. Draw the circuit it should consist of ROM and D-FFs and write the first 5 lines of the ROM program
A clocked Mealy sequential network has one input (X) and two outputs (Z1Z2).If Circuit receives (0,1,0) input while haven't received the (1,0,0) input before circuit would give Z1 = 1 result. For every (1,0,0) input received circuit would give Z2 = 1 output. If ever the circuit's Z2 output becomes Z2=1 circuit's Z1 output wont be Z1=1 afterwards but if Z1 output becomes Z1=1 it won't affect Z2 outputs capability of resulting 1. Draw the circuit it should consist of ROM and D-FFs and write the first 5 lines of the ROM program
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
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A clocked Mealy sequential network has one input (X) and two outputs (Z1Z2).If Circuit receives (0,1,0) input while haven't received the (1,0,0) input before circuit would give Z1 = 1 result. For every (1,0,0) input received circuit would give Z2 = 1 output. If ever the circuit's Z2 output becomes Z2=1 circuit's Z1 output wont be Z1=1 afterwards but if Z1 output becomes Z1=1 it won't affect Z2 outputs capability of resulting 1. Draw the circuit it should consist of ROM and D-FFs and write the first 5 lines of the ROM program
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