A 5-stage pipelined processor has the stages: Instruction Fetch (IF), Instruction Decode  (ID), Operand Fetch (OF), Execute (EX) and Write Operand (WO). The IF, ID, OF, and WO stages take 1 clock cycle each for any instruction. The EX stage takes 1 clock cycle for ADD  and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV  instruction. Operand forwarding is used in the pipeline (for data dependency, OF stage of the  dependent instruction can be executed only after the previous instruction completes EX).  What is the number of clock cycles needed to execute the following sequence of instructions?  MUL R2,R10,R1  DIV R5,R3,R4  ADD R2,R5,R2   SUB R5,R2,R6

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A 5-stage pipelined processor has the stages: Instruction Fetch (IF), Instruction Decode 
(ID), Operand Fetch (OF), Execute (EX) and Write Operand (WO). The IF, ID, OF, and WO
stages take 1 clock cycle each for any instruction. The EX stage takes 1 clock cycle for ADD 
and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV 
instruction. Operand forwarding is used in the pipeline (for data dependency, OF stage of the 
dependent instruction can be executed only after the previous instruction completes EX). 
What is the number of clock cycles needed to execute the following sequence of instructions? 
MUL R2,R10,R1 
DIV R5,R3,R4 
ADD R2,R5,R2 
 SUB R5,R2,R6 

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