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7. Mark each statement below as true or false. Explain your reasoning. Provide a counterexample if the statement is false. (a) A two-way set associative cache always has a lower miss rate than a direct mapped cache with the same block size and total capacity. (b) A 16 KiB direct mapped cache always has a lower miss rate than an 8 KiB direct mapped cache with the same block size.

7. Mark each statement below as true or false. Explain your reasoning. Provide a counterexample if the statement is false. (a) A two-way set associative cache always has a lower miss rate than a direct mapped cache with the same block size and total capacity. (b) A 16 KiB direct mapped cache always has a lower miss rate than an 8 KiB direct mapped cache with the same block size.

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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7. Mark each statement below as true or false. Explain your reasoning. Provide a counterexample if the statement is false. (a) A two-way set associative cache always has a lower miss rate than a direct mapped cache with the same block size and total capacity. (b) A 16 KiB direct mapped cache always has a lower miss rate than an 8 KiB direct mapped cache with the same block size. (c) An instruction cache with a 32-byte block size usually has a lower miss rate than an instruction cache with an 8-byte block size, given the same degree of associativity and total сараcity.
Transcribed Image Text:7. Mark each statement below as true or false. Explain your reasoning. Provide a counterexample if the statement is false. (a) A two-way set associative cache always has a lower miss rate than a direct mapped cache with the same block size and total capacity. (b) A 16 KiB direct mapped cache always has a lower miss rate than an 8 KiB direct mapped cache with the same block size. (c) An instruction cache with a 32-byte block size usually has a lower miss rate than an instruction cache with an 8-byte block size, given the same degree of associativity and total сараcity.
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