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5. Design 3 bit: Synchronous Down counter with D flipflops.

5. Design 3 bit: Synchronous Down counter with D flipflops.

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4. A PN flip-flop has four operations: set to 1, complement, no change and clear to 0, when inputs P and N are 00, 01, 10, and 11, respectively. (a) Tabulate the characteristic table. (b) Tabulate the excitation table. (c) Show how the PN flip-flop can be converted to a T flip-flop 5. Design 3 bit: Synchronous Down counter with D flipflops. 6. (a) Design PLA for the following Boolean functions fi(A, B, C)-E(0, 2, 3, 4,7) and (A, B, C) = Em(1, 5, 6, 7). (5 M) (5 M) (b) Design CMOS circuit for the Boolean function Y A + (B+C)D. ASUS
Transcribed Image Text:4. A PN flip-flop has four operations: set to 1, complement, no change and clear to 0, when inputs P and N are 00, 01, 10, and 11, respectively. (a) Tabulate the characteristic table. (b) Tabulate the excitation table. (c) Show how the PN flip-flop can be converted to a T flip-flop 5. Design 3 bit: Synchronous Down counter with D flipflops. 6. (a) Design PLA for the following Boolean functions fi(A, B, C)-E(0, 2, 3, 4,7) and (A, B, C) = Em(1, 5, 6, 7). (5 M) (5 M) (b) Design CMOS circuit for the Boolean function Y A + (B+C)D. ASUS
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