5. a. b. Explain Set Associative Mapping Cache Function? Consider a 2-way set associative mapped cache of size 16 KB with block size 256 bytes. The size of main memory is 128 KB. Find- 1. Number of bits in tag 2. Tag directory size

5. a. b. Explain Set Associative Mapping Cache Function? Consider a 2-way set associative mapped cache of size 16 KB with block size 256 bytes. The size of main memory is 128 KB. Find- 1. Number of bits in tag 2. Tag directory size

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Question

5. a.
b.
Explain Set Associative Mapping Cache Function?
Consider a 2-way set associative mapped cache of size 16 KB with block size 256
bytes. The size of main memory is 128 KB. Find-
1. Number of bits in tag
2. Tag directory size

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We are given a list of 64-bit memory address references, given as word addresses. Ox03, Oxb4, Ox2b, 0x02, Oxbf, Ox58, Oxbe, OxOe, Oxb5, Ox2c, Oxba, Oxfd (A) For each of these references, identify the binary word address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list whether each reference is a hit or a miss, assuming the cache is initially empty. (B) For each of these references, identify the binary word address, the tag, the index, and the offset given a direct-mapped cache with two- word blocks and a total size of eight blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. (C) You are asked to optimize a cache design for the given references (i.e. addresses). There are three direct-mapped cache designs possible, all with a total of eight words of data: (i) Cache1 has 1-word blocks, (ii) Cache2 has 2-word blocks, and (iii) Cache3 has 4-word blocks.
1. Suppose we have a 32KB direct-mapped data cache with 32-byteblocks.a) Show how a 32-bit memory address is divided into tag, index andoffset. Show clearly how many bits are in each field.b) How many total bits are there in this cache?
.2: Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, 253 For each of these references, identify the binary address, the tag, and the index given a direct- mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 2-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 4-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty.
Cache Mapping a. A computer system has a main memory with 128 blocks and a cache with 32 blocks. If it uses direct mapping, how many main memory blocks can be mapped to a single cache block? b. In a set-associative cache with 64 blocks and divided into 4 sets, determine the associativity of each set. c. For a fully associative cache with 256 blocks, how many sets are there?
Consider a cache with 128 blocks. The block size is 32 bytes. Find the number of tag bits, index bits, and offset bits in a 32-bit address if you design it as a) Direct-mapped b) 8-way Set Associative
Assume that you have a direct-mapped cache with 16 indices and each block can contain 32 words. Assuming that each bytes address is 32 bits long (and a word is 32 bits), answer the following questions: a). How many bits in each address are used for its tag? bits b). Compute the total number of bits required to implement this cache, including valid bits, tag bits and bits used for data. bits
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Consider a 2-block fully associative cache. The following blocks from main memory are accessed which need to be mapped to cache: P, Q, P, R. Which block is replaced from the cache when the last block (block R) is accessed? Assume FIFO replacement policy.
This chapter explains how to implement the four cache replacement policies.
7. Show the final data and tags of the direct-mapped cache shown below for the given memory contents and data access sequence. As shown, you have 8-bit addresses and 4 bytes of data in each block. You can assume write-through and write-allocate write strategies on write hits and misses respectively. Data Access Sequence Address Data 00 01 11 00 00 10 10 00 00 10 01 00 00 01 00 00 00 11 01 00 00 10 10 00 00 01 11 00 00 10 01 00 00 10 00 00 00 10 10 00 Op. lw lw SW lw SW lw lw SW lw lw hits = misses = 32 642 124 I 00 01 10 11 Direct-Mapped Cache V Tag Data hit rate = miss rate = Memory Address 00 00 10 00 00 00 11 00 00 01 00 00 00 01 01 00 00 01 10 00 00 01 11 00 00 10 00 00 00 10 01 00 00 10 10 00 00 10 11 00 00 11 00 00 00 11 01 00 Data 435 9 47 13 7586 86 43 48 673 4 972 1003