4. Using the operations corresponding to the gates in the gate table, derive a minimal (with respect to literals) expression for the number of days in a given month. The expression has five bits of input: • m3, m2, m₁, mo: a four-bit number indicating the month (0001 is January, 0010 is February, etc.) leap: a single bit that true if and only if it is a leap year The expression has five output bits: d4, d3, d2, d1, do: a five-bit number indicating the number of days in the given month. See Thirty Days Hath September for the rules. ● ●

4. Using the operations corresponding to the gates in the gate table, derive a minimal (with respect to literals) expression for the number of days in a given month. The expression has five bits of input: • m3, m2, m₁, mo: a four-bit number indicating the month (0001 is January, 0010 is February, etc.) leap: a single bit that true if and only if it is a leap year The expression has five output bits: d4, d3, d2, d1, do: a five-bit number indicating the number of days in the given month. See Thirty Days Hath September for the rules. ● ●

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Q6. For the Boolean function F = xy'z + x'y'z + w'xy + wx'y + wxy (a) Obtain the truth table of F (b) Draw the logic diagram, using the original Boolean expression. (c) Use Boolean algebra to simplify the function to a minimum number of literals. Obtain the truth table of the function from the simplified expression and show that it is the same as the one in part (a). (d) (e) Draw the logic diagram from the simplified expression, and compare the total number of gates with the diagram of part (b).
6. For the following Verilog code, draw the corresponding circuit diagram for "bigMod". Your circuit should only involve standard gates (AND, OR, NAND, NOR, XOR, Inverter), and the variable names Val, X, Y, and Z. DO NOT SIMPLIFY THE CIRCUIT. Note: all of the code is legal Verilog, with no errors. module tstMod (F, A, B, C); output logic F; input logic A, B, C; assign F endmodule = (A & ~B & C) | (A & C) | ~B; module bigMod (Val, X, Y, output logic Val; input logic X, Y, Z; logic T; Z); .C (Y)); tstMod T1 (.F (T), .A (X), .B (1'bl), tstMod T2 (.F (Val), .A(Z), .B (T), .C (X)); endmodule
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