4. Refer to figure 30-3. Increasing the input signal to a high value would result in a. normal undistorted circuit operation. b. a higher the normal input impedance. c. excessive loading of the VDD power supply. d. reduced input impedance and distorted output signal.
4. Refer to figure 30-3. Increasing the input signal to a high value would result in a. normal undistorted circuit operation. b. a higher the normal input impedance. c. excessive loading of the VDD power supply. d. reduced input impedance and distorted output signal.
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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Question 4
![61
Review Questions
. Connect the circuit shown in figure 30-3. Adjust the signal generator for a 0.3 VPK-PK.
21. Place CM switch 17 in the ON position. Which is the effect on circuit gain when load resistor
a. Circuit gain is increased.
b.Circuit gain is not affected.
c. Circuit gain is decreased.
d. Circuit gain becomes negative.
R3
8002
D.
G
0.022 MF
GEN
R1
IM
R2
HF
80027
Figure 30-3. JFET voltage amplifier
2. Place CM switch 17 in the OFF position and CM switch 18 in the ON position. What is t
load resistor R3 is decreased?
a. Circuit gain is increased.
b. Circuit gain is not affected.
c. Circuit gain is decreased.
d. Circuit gain becomes negative.
3. Refer to figure 30-3. Te purpose of C2 is to
a. control the amount of gate current.
b. increase degenerative feedback.
c. decrease degenerative feedback.
d. bypass the VDD power supply.
4. Refer to figure 30-3. Increasing the input signal to a high value would result in
a. normal undistorted circuit operation.
b. a higher the normal input impedance.
c. excessive loading of the VDD power supply.
d. reduced input impedance and distorted output signal.
5. The value of R1 in figure 30-3 is set at 1M to keep the
a. circuit input impedance below 100
b.
circuit input
imner](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fc33de430-6637-4884-a8e7-9ced9f08e247%2Fe208f232-0d4d-44b4-87e1-1cac8162ddf1%2Fy4aqioo_processed.jpeg&w=3840&q=75)
Transcribed Image Text:61
Review Questions
. Connect the circuit shown in figure 30-3. Adjust the signal generator for a 0.3 VPK-PK.
21. Place CM switch 17 in the ON position. Which is the effect on circuit gain when load resistor
a. Circuit gain is increased.
b.Circuit gain is not affected.
c. Circuit gain is decreased.
d. Circuit gain becomes negative.
R3
8002
D.
G
0.022 MF
GEN
R1
IM
R2
HF
80027
Figure 30-3. JFET voltage amplifier
2. Place CM switch 17 in the OFF position and CM switch 18 in the ON position. What is t
load resistor R3 is decreased?
a. Circuit gain is increased.
b. Circuit gain is not affected.
c. Circuit gain is decreased.
d. Circuit gain becomes negative.
3. Refer to figure 30-3. Te purpose of C2 is to
a. control the amount of gate current.
b. increase degenerative feedback.
c. decrease degenerative feedback.
d. bypass the VDD power supply.
4. Refer to figure 30-3. Increasing the input signal to a high value would result in
a. normal undistorted circuit operation.
b. a higher the normal input impedance.
c. excessive loading of the VDD power supply.
d. reduced input impedance and distorted output signal.
5. The value of R1 in figure 30-3 is set at 1M to keep the
a. circuit input impedance below 100
b.
circuit input
imner
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