4. A 80 MHz clock frequency mclk is provided to two cascaded 12-bit counters as connected in the logic diagram shown below. Assuming the clear input clr is low, what is the output clock frequency clk2 of the second counter on the right? mlk 80 MHz CLK Q[6] clk1 CLK Q[8] clk2 clr CLR CLR

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4. A 80 MHz clock frequency mclk is provided to two cascaded 12-bit counters as connected in the
logic diagram shown below. Assuming the clear input clr is low, what is the output clock frequency
clk2 of the second counter on the right?
mlk 80 MHz
CLK
Q[6]
clk1
CLK
Q[8]
clk2
clr
CLR
CLR
Transcribed Image Text:4. A 80 MHz clock frequency mclk is provided to two cascaded 12-bit counters as connected in the logic diagram shown below. Assuming the clear input clr is low, what is the output clock frequency clk2 of the second counter on the right? mlk 80 MHz CLK Q[6] clk1 CLK Q[8] clk2 clr CLR CLR
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