4- Which of the following data hazards can cause stalls in in-order pipelines: A-Read-After-Read B-Write-After-Read C-Read-After-Write D- (None) 5- For the same cache size, increasing cache associativity reduces: A-Capacity misses B-Conflict misses C- Cold misses D- (All Answers) 6- For a fully-associative cache, increasing cache size reduces: A-Capacity misses B-Conflict misses C- Cold misses D- (All Answers)

4- Which of the following data hazards can cause stalls in in-order pipelines: A-Read-After-Read B-Write-After-Read C-Read-After-Write D- (None) 5- For the same cache size, increasing cache associativity reduces: A-Capacity misses B-Conflict misses C- Cold misses D- (All Answers) 6- For a fully-associative cache, increasing cache size reduces: A-Capacity misses B-Conflict misses C- Cold misses D- (All Answers)

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Concept explainers

Fundamentals of memory

A collection of connected storage devices form the memory unit. It is a space to store data and instructions required for processing. Information is stored in a memory unit in the form of bits. There are two types of memory namely:

Question

Answer 4, 5 and 6 please

T-Mobile
A- Refresh
A-14.5
1- Emerging NVMs are expected to replace DRAM because of their:
A-Density/Capacity B-Low power C-Speed
D- (A and B)
2- The DRAM operation that is required to adjust the bitlines' voltage before
read/write operation is called:
B- Precharge
3- To mitigate control hazards, processor cores use:
A- Prefetching B-Branch delay slots C- Branch prediction D- (B and C)
4- Which of the following data hazards can cause stalls in in-order pipelines:
A-Read-After-Read B-Write-After-Read C-Read-After-Write D- (None)
5- For the same cache size, increasing cache associativity reduces:
A-Capacity misses B-Conflict misses C- Cold misses D- (All Answers)
6- For a fully-associative cache, increasing cache size reduces:
A-Capacity misses B-Conflict misses C-Cold misses D- (All Answers)
7- The inclusion property that requires checking only last-level caches for
coherence transactions is:
A-Inclusive
A-Modified
6:29 PM
Today
6:08 PM
B-Shared
C-Activation D- Interleaving
B- Non-inclusive C- Exclusive
D- (B and C)
8- In MSI coherence protocol, one of the following states also implies that the
cache block exists in only one of the caches in the system:
C- Dirty
D- (None)
9- Assume we have a single-level cache hierarchy system that runs an
application. If you know that L1 cache hit time is 5 cycle, hit rate is 55% and
memory latency is 100 cycles. The AMAT is:
B-60
C- 5.55
@ 100% 2
D-50
y requase the studieAR) dep
ommit
i
Edit
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