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- A 74LS139 2-to-4 code is used to partition the memory space of an MC68008 into 4 quadrant, ROM, RAM, PER (for Synchronous devices) and the 4th is reserved for future provision. Write the address range of the RAM. And compute the addresses per location in ROM if is 64 KBGiven the RISC instruction xorcc %i1, 885, %g4 Answer the following questions regarding the 32-bits of this instruction (all answers should be binary one's and zero's and should NOT contain any spaces): a) What are the two most significant bits of this instruction? b) What are the five destination register bits? c) What are the six operation bits? d) What are the five first operand bits? e) What is the value of bit 13? f) What are the second operand bits stored in instruction bits 12 down to 0? (must be appropriate size in binary)The table shows a segment of primary memory from a Von Neumann model computer. Address Contents 000000 11101101 000001 10101010 000010 11011011 000011 11101110 000100 11111011 000101 00011000 (a) The program counter contains the data 000011. (i) State the data in the memory address register (MAR). (ii) State the data in the memory data register (MDR). A Write Operation has been carried out using the data 11000000 in the location 000100. (b) State the contents of MAR and MDR. MAR: MDR:
- Find the machine code for the following instruction in RISC-V. Assume all instructions are labeled sequentially, for example, I1, I2, I3, …, I200. I10 : BGE x10, x20, I100For the 8086 memory segment (011A) h with an offset (2B35) h, the memory address isGiven 16-bit instructions, is it possible to use expanding opcodes to allow the following to be encoded assuming we have a total of 32 registers? If so, show the encoding. If not, explain why it is not possible. 60 instructions with 2 register operands3 instructions with one 10-bit address30 instructions with 1 register operands26 instructions with zero operands
- Choose the right answer from among the following statements. 1) According to the 80/20 rule, 80 percent of the instructions are performed and only 20 percent of the instructions are generated. 2) The external bus in the von Neumann architecture is only for the purpose of data memory storage.Computer Science Y86-64 Question 2: Try to write the machine code encoding of the assembly instruction. mrmovq 0x15F(%rbx), %rax Tips: It has a little-endian byte ordering. Please show the full steps.A certain computer has a memory of 1M words, and each word is 32 bits long. Each instruction is 32 bits long and is consisted of an opcode field, a register address field to specify one of 32 registers, and a memory address field. How large must the register field be? How large must the address field be? How many different opcodes can be supported by this format? Show your reasoning
- a) Show how the memory of an 8086 µP is organized. 0) Explain how in the 8086 minimum mode a word of data will be written to memory starting at address B2023H? O Draw one 8088 minimum mode memory read bus cycle showing clearly the memory control signals with their logic levels along the 4-T states bus cycle. diggram3. For each instruction in the table, write 8 hexadecimal digits that represent the 32 bits in the destination register after the instruction is executed. Assume s0 is 0x98AB3C6A, s1 is 0x20503666. Instructions to, 50, s1 t1, so, s1 t2, so, s1 t3, 50, 51 addi t4, 50, 0x210 wwwwwww andi t5, 50, -16 add and or xor slli t6, 50, 12 srai s2, 50, 8 Dest. reg. in 8 hexadecimal digitsAnswer by true or false 1-Registers inside the CPU can be 8-bit, 16-bit, 32-bit or even 64-bit depending on the CPU * 2-In 8086 microprocessor Pins AD0 – AD15 are used for the data bus. * 3-In 8086 microprocessor Pins AD0 – AD15 are used for the address bus. *