3. Given a 32-byte cache (byte-addressable, initially empty) and a sequence of access address (6)10, (24)10, (34)10, (0)10, (28)10, (4)10, please derive the corresponding hit/miss sequence for each of the following cache designs. For each design, draw the same table in your answer sheet and fill out the table vou draw.
3. Given a 32-byte cache (byte-addressable, initially empty) and a sequence of access address (6)10, (24)10, (34)10, (0)10, (28)10, (4)10, please derive the corresponding hit/miss sequence for each of the following cache designs. For each design, draw the same table in your answer sheet and fill out the table vou draw.
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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1082_B_3_CA
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Transcribed Image Text:Given a 32-byte cache (byte-addressable, initially empty) and a sequence of access addresses:
(6)10, (24)10, (34)10, (0)10, (28)10, (4)10, please derive the corresponding hit/miss sequence for each
of the following cache designs. For each design, draw the same table in your answer sheet and fill
out the table you draw.
3.

Transcribed Image Text:(a) 16 bytes per block, direct-mapped (6%)
Address
Cache index Hit or miss?
24
34
28
4
(b) 8 bytes per block, 2-way set associative (6%)
Address
Cache index Hit or miss?
24
34
28
4
(c) 8 bytes per block, fully associative (6%)
Cache index Hit or miss?
Address
6.
24
34
28
4
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