3) In the circuit shown in Figure 2, assuming ideal op amp properties and no loading effects, answer the following: a) What is the gain of stage Van 1, A₂₁ = Vi b) What is the gain of stage 2, Av2 = Vo? Va c) What is the overall gain Av = 40? Vi Vi R2 00 R3 www R1 www Stage www R4 Stage 2 Vo Figure 2 Circuit for question 4 d) Using the following R₁ = 10 kn, R₂ = 100 kn, C₁ = 16 nF, design R3 and R4 such that input V₂ (t) = 1.0 · sin (2π · 72 t) [V] has an output amplitude of 12[V].

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Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
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Solution for a-c previously posted, please work through part d

3) In the circuit shown in Figure
2, assuming ideal op amp
properties and no loading
effects, answer the following:
a) What is the gain of stage
1, Av₁ = Van
V₁
b) What is the gain of stage
2, A₂₂ = Von
Va
c) What is the overall gain
A₂ = Vo
Vi
d) Using the following R₁ = 10
10
input V₂ (t) = 1.0 sin (2n
.
Vi
C1
R2
FLE
Va
R3
Stage 1
kn, R₂
R2
ΚΩ,
www
R1
+
www
R4
Stage 2
Vo
Figure 2 Circuit for question 4
= 100 ΚΩ, C1 16 nF, design R3 and R4 such that
72-t) [V] has an output amplitude of 12[V].
Transcribed Image Text:3) In the circuit shown in Figure 2, assuming ideal op amp properties and no loading effects, answer the following: a) What is the gain of stage 1, Av₁ = Van V₁ b) What is the gain of stage 2, A₂₂ = Von Va c) What is the overall gain A₂ = Vo Vi d) Using the following R₁ = 10 10 input V₂ (t) = 1.0 sin (2n . Vi C1 R2 FLE Va R3 Stage 1 kn, R₂ R2 ΚΩ, www R1 + www R4 Stage 2 Vo Figure 2 Circuit for question 4 = 100 ΚΩ, C1 16 nF, design R3 and R4 such that 72-t) [V] has an output amplitude of 12[V].
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