3 Define Scheme procedures to simulate the logic dezsign given in the diagram in Figure 3. The procedures must follow the design in the figure and call the gate procedures that you defined in the previous questions and must return a pair with two elements ¹(c. s), where s is the binary sum of a, b, and x (carry in), while c is the carry-out. You will implement the procedure in three steps using three procedures, as listed below. 3.1 Write a procedure (half-adder x a b) to generate (return) the sum bit s. The upper half of Fig. 3 that computes sum. 3.2 Write a procedure (carry-out x a b) to generate (return) the carryOut bit c. The lower half of Fig. 3. 3.3 Write a procedure (full-adder x a b) to generate the pair output (c. s), where s is the output of the half-adder procedure and c is the output of the carry-out procedure. A full-adder is also called a one-bit adder. a b carryin THE PO D sum carryOut Figure 3. The logic design of a one-bit full adder Verify your procedure by exhaustive testing: Use all valid inputs to test the procedure. There are eight valid inputs: (full-adder 0 0 0) (full-adder 0 0 1) (full-adder 0 1 0) (full-adder 0 1 1) (full-adder 1 0 0) (full-adder 1 0 1) (full-adder 1 1 0) (full-adder 1 1 1) The test cases and expected outputs are given in the code template file. Do not remove or edit these lines.
3 Define Scheme procedures to simulate the logic dezsign given in the diagram in Figure 3. The procedures must follow the design in the figure and call the gate procedures that you defined in the previous questions and must return a pair with two elements ¹(c. s), where s is the binary sum of a, b, and x (carry in), while c is the carry-out. You will implement the procedure in three steps using three procedures, as listed below. 3.1 Write a procedure (half-adder x a b) to generate (return) the sum bit s. The upper half of Fig. 3 that computes sum. 3.2 Write a procedure (carry-out x a b) to generate (return) the carryOut bit c. The lower half of Fig. 3. 3.3 Write a procedure (full-adder x a b) to generate the pair output (c. s), where s is the output of the half-adder procedure and c is the output of the carry-out procedure. A full-adder is also called a one-bit adder. a b carryin THE PO D sum carryOut Figure 3. The logic design of a one-bit full adder Verify your procedure by exhaustive testing: Use all valid inputs to test the procedure. There are eight valid inputs: (full-adder 0 0 0) (full-adder 0 0 1) (full-adder 0 1 0) (full-adder 0 1 1) (full-adder 1 0 0) (full-adder 1 0 1) (full-adder 1 1 0) (full-adder 1 1 1) The test cases and expected outputs are given in the code template file. Do not remove or edit these lines.
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Transcribed Image Text:3
Define Scheme procedures to simulate the logic dezsign given in the diagram in Figure 3.
The procedures must follow the design in the figure and call the gate procedures that you
defined in the previous questions and must return a pair with two elements ' (c. s),
where s is the binary sum of a, b, and x (carry in), while c is the carry-out. You will
implement the procedure in three steps using three procedures, as listed below.
3.1 Write a procedure (half-adder x a b) to generate (return) the sum bit s. The upper half of
Fig. 3 that computes sum.
3.2 Write a procedure (carry-out x a b) to generate (return) the carryOut bit c. The lower half of
Fig. 3.
3.3 Write a procedure (full-adder x a b) to generate the pair output (c. s), where s is the output
of the half-adder procedure and c is the output of the carry-out procedure. A full-adder is
also called a one-bit adder.
a
b
carryin
THE
D
sum
carryOut
Figure 3. The logic design of a one-bit full adder
Verify your procedure by exhaustive testing: Use all valid inputs to test the procedure.
There are eight valid inputs:
(full-adder 0 0 0)
(full-adder 0 0 1)
(full-adder 0 1 0)
(full-adder 0 1 1)
(full-adder 1 0 0)
(full-adder 1 0 1)
(full-adder 1 1 0)
(full-adder 1 1 1)
The test cases and expected outputs are given in the code template file. Do not remove or
edit these lines.
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