2. You have to design a vending machine for a 4 Tk product. The vending machine can only accept inputs: no money (can be represented as input w=00), Tk 1 (can be represented as input w=01), and Tk 3 (can be represented as input w=10). Once an acceptable input is more than or equal to 4 Tk, the machine immediately generates an output Q=1, goes back to the initial state, and gives back the change (if required). Change in Tk is represented as 2 digit binary output c={c1c2}. Output c has to be calculated
2. You have to design a vending machine for a 4 Tk product. The vending machine can only accept inputs: no money (can be represented as input w=00), Tk 1 (can be represented as input w=01), and Tk 3 (can be represented as input w=10). Once an acceptable input is more than or equal to 4 Tk, the machine immediately generates an output Q=1, goes back to the initial state, and gives back the change (if required). Change in Tk is represented as 2 digit binary output c={c1c2}. Output c has to be calculated
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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![2. You have to design a vending machine
for a 4 Tk product. The vending machine
can only accept inputs: no money (can be
represented as input w=00), Tk 1 (can be
represented as input w=01), and Tk 3
(can be represented as input w=10).
Once an acceptable input is more than or
equal to 4 Tk, the machine immediately
generates an output Q=1, goes back to
the initial state, and gives back the
change (if required). Change in Tk is
represented as 2 digit binary output
c={c1c2}. Output c has to be calculated
and initialized. Suppose, changes are
1Tk, 2Tk (assumed). Initialize 1Tk as
c=00
and
2Tk
as
c=01. Reset
functionality is not mandatory. Draw the
state diagram, the state-assigned table,
write the Verilog code, run simulations
and verify your answer.
t t t t. t. t. t t. t. t. t. t.
1 3 0310| 3 | 3 0|3 |0
00 01 10 00 10 01 00 10 10 00 10 00
010|010 0
clock
Tk input
10 | 01
1
0|00
?
?
?
?
?
?
?
?
?
?
?
Expected Output:
The timing diagram should contain
waveforms as described in the table. The
clock period should be 10 ns. The
discussion must contain a state diagram,
state
assigned
table,
and
brief
explanations of all high output situations
e.g. Q
|high during t3, to, and to clock
cycles. Briefly explain these situations in
light of the problem statement and your
derived state diagram/state assigned
table. Also, initialize and complete output
С.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F81b21769-b8ca-4702-80fa-97985e8c915e%2Fa83c0165-ed0a-406d-9dab-09e61a16f76b%2Fzvzdwr_processed.png&w=3840&q=75)
Transcribed Image Text:2. You have to design a vending machine
for a 4 Tk product. The vending machine
can only accept inputs: no money (can be
represented as input w=00), Tk 1 (can be
represented as input w=01), and Tk 3
(can be represented as input w=10).
Once an acceptable input is more than or
equal to 4 Tk, the machine immediately
generates an output Q=1, goes back to
the initial state, and gives back the
change (if required). Change in Tk is
represented as 2 digit binary output
c={c1c2}. Output c has to be calculated
and initialized. Suppose, changes are
1Tk, 2Tk (assumed). Initialize 1Tk as
c=00
and
2Tk
as
c=01. Reset
functionality is not mandatory. Draw the
state diagram, the state-assigned table,
write the Verilog code, run simulations
and verify your answer.
t t t t. t. t. t t. t. t. t. t.
1 3 0310| 3 | 3 0|3 |0
00 01 10 00 10 01 00 10 10 00 10 00
010|010 0
clock
Tk input
10 | 01
1
0|00
?
?
?
?
?
?
?
?
?
?
?
Expected Output:
The timing diagram should contain
waveforms as described in the table. The
clock period should be 10 ns. The
discussion must contain a state diagram,
state
assigned
table,
and
brief
explanations of all high output situations
e.g. Q
|high during t3, to, and to clock
cycles. Briefly explain these situations in
light of the problem statement and your
derived state diagram/state assigned
table. Also, initialize and complete output
С.
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