**Digital Logic Design: Decoders Exercise**### Problem StatementThe 2-to-4 decoders with **active-low** outputs are available as building blocks. Each block has two enable inputs (EA, EB), two address lines (A1, A0), and 4 outputs (M0, M1, M2, M3). EA is active-high, EB is active-low. Both enable inputs must have active levels (EA=1, EB=0) in order to enable the decoder outputs.### Tasks:**2a) Show the truth table for the decoder block:** - 4 inputs: EA, EB, A1, A0 - 4 outputs: M0 to M3**2b) Construct the 4-to-16 line decoder with active-low outputs:** - Use any number of the 2-to-4 decoders as building blocks. - No inverters are available. - Show the schematic.**2c) Construct the 3-to-8 line decoder with active-high outputs:** - Use any number of the 2-to-4 decoders as building blocks. - Any number of inverters are available. - Show the schematic.### Key Points:- Inputs and outputs of all decoders, including building blocks, must be denoted with A0, A1, A2, A3 (if applicable) for inputs and 0, 1, 2, ..., 15 (if applicable) for outputs.- No inputs should be left floating unconnected.- Unused enable inputs must be connected to appropriate logic levels (Vdd or ground).This problem presents an exercise in understanding and creating decoders using fundamental digital logic principles. You are expected to demonstrate your knowledge of how decoders work and your ability to construct complex decoding circuits using basic building blocks.

Answered: Image /qna-images/answer/b673342b-15df-4ae0-806e-3edf7149ce4a.jpg

2. The 2-to-4 decoders with active-low outputs are available as building blocks. Each block has two enable inputs (EA, EB), two address lines (A1, AO) and 4 outputs (MO, M1, M2, M3). EA is active-high, EB is active-low. Both enable inputs must have active levels (EA=1, EB=0) in order to enable the decoder outputs. 2a) Show the truth table for the decoder block: 4 inputs are EA, EB, A1, AO; 4 outputs are MO to M3. 2b) Construct the 4-to-16 line decoder with active-low outputs using any number of the 2-to-4 decoders as building blocks. No inverters are available. Show the schematic. 2c) Construct the 3-to-8 line decoder with active-high outputs using any number of the 2-to-4 decoders as building blocks. Aby number of inverters are available. Show the schematic. Inputs and outputs of all decoders including building blocks have to be denoted with A0, A1, A2, A3 (if applicable) for inputs and 0, 1, 2,...,15 (if applicable) for outputs. No inputs should be left floating unconnected). Unused enable inputs must be connected to appropriate logic levels (Vdd or ground).

2. The 2-to-4 decoders with active-low outputs are available as building blocks. Each block has two enable inputs (EA, EB), two address lines (A1, AO) and 4 outputs (MO, M1, M2, M3). EA is active-high, EB is active-low. Both enable inputs must have active levels (EA=1, EB=0) in order to enable the decoder outputs. 2a) Show the truth table for the decoder block: 4 inputs are EA, EB, A1, AO; 4 outputs are MO to M3. 2b) Construct the 4-to-16 line decoder with active-low outputs using any number of the 2-to-4 decoders as building blocks. No inverters are available. Show the schematic. 2c) Construct the 3-to-8 line decoder with active-high outputs using any number of the 2-to-4 decoders as building blocks. Aby number of inverters are available. Show the schematic. Inputs and outputs of all decoders including building blocks have to be denoted with A0, A1, A2, A3 (if applicable) for inputs and 0, 1, 2,...,15 (if applicable) for outputs. No inputs should be left floating unconnected). Unused enable inputs must be connected to appropriate logic levels (Vdd or ground).

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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