2. For the transmission line below, determine the impedances. (Zo = 50, f = 2 GHz) (a) Input impedance to the right of the junction (ZA) (b) Input impedance to the lower side of the junction (ZB) (c) Zin -0.110A- Zi in ZB ZA 50 Ω 50 Ω 0.095A + 60 Ω 0.995 PF

Q2: For the pole-zero diagram shown in Figure below. Calculate and plot the magnitude frequency and phase responses, where the magnitudes of poles and zeros from the origin are 0.5 and 0.8 respectively. Im(2) Figure Q2 Pole-Zero plot Re(z)

RLC Series AC Circuits• Calculate the impedance, phase angle, resonant frequency, power, power factor, voltage, and/or current in a RLCseries circuit.• Draw the circuit diagram for an RLC series circuit.• Explain the significance of the resonant frequency.

Identify all the TRUE statements below. A) At resonance, there is no net voltage drop across all the reactive elements of the circuits. B) To minimize the impact of capacitance in an AC series circuit, set its value close to zero. C) To minimize the impact of inductance in an AC series circuit, set its value close to zero. D) At resonance, Xc and XL are always zero. E) At resonance, power is maximized and phase shift is zero. F) At resonance, X = XL. %3D G) At resonance net reactance is zero. H) Capacitance is the measure of how difficult it is to store charge for a given voltage. The higher the capacitance, the more voltage it takes to store charge on it. F hp H. B. C. E.

Qualitative AC Circuits R 1. Consider reading the voltage across the capacitor in the drawn circuit'. Here the voltage v. across the capacitor can be taken as the output of EO Frequency w Vout = ve the circuit. Will the output of this circuit be larger for high frequency input or low frequency input? Explain why.

The average power absorbed by a resonant circuit is at a minimum at resonance.  True  False

i know b and d is true, idk about the rest

Identify all the TRUE statements below. A) At resonance, there is no net voltage drop across all the reactive elements of the circuits. B) To minimize the impact of capacitance in an AC series circuit, set its value close to zero. C) To minimize the impact of inductance in an AC series circuit, set its value close to zero. D) At resonance, X, and XL are always zero. E) At resonance, power is maximized and phase shift is zero. F) At resonance, Xc = Xµ. G) At resonance net reactance is zero. H) Capacitance is the measure of how difficult it is to store charge for a given voltage. The higher the capacitance, the more voltage it takes to store charge on it.

communucation systems help pls can you do i and ii ( if its possible iii also would be very  grateful)

3) The local average power delay profile is found to be w w w w 2K P(r,) = EG+}-»") 10-36(+ – n10-) 10-28 n=1 a. Sketch the power delay profile of the channel. mww m b. What is the rms delay spread of the channel (in terms of K)? 1+2+3+ ...+ K = K(K+1) 2 , 12 + 22 + 32 + ..+ K2 = K(K+1)(2K+1) Hint: