2. Consider a fully-connected network with 1280 inputs, two hidden layers with 512 units each, and 32 output classes. Assume that all weights and activations are stored as 32-bit values. A. How much parameter storage is required for this model? B. Running this model on an 80MHZ processor that can compute 1 MAC every 4 cycles, how long will one inference take (answer in ms). C. How much temporary storage (SRAM) is required to run this model?
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- Q1. Consider that the up system consists of two memory sections, the SRAM and the EPROM. The up clock system is 5 MHz and the bus cycle is equal to 4-clocks of the system clock pulses. For reading process, suppose that the waiting time of SRAM equals % waiting time of EPROM. If you know that, the total time requires for reading both memory types 1900 ns, what is the total waiting time requires for reading 128 bytes from the SRAM and the total waiting time requires for reading 512 bytes of EPROM? How many wait states require for reading each section of memory? Sketch the required circuit for generating the required number of the wait states.Implement a multi-layer perceptron from scratch in python. This would include the following1 Write activation functions.2 Forward propagate the input.3. Backward propagate the error.4 Train the network using stochastic gradient descent.5 Predict the output for a given test sample and compute the accuracy.please no chatgpt answer . Consider a demand-paging system with a paging disk that has an average access and transfer time of 20 milliseconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference, if the page-table entry is in the associative memory. Assume that 80 percent of the accesses are in the associative memory and that, of those remaining, 10 percent (or 2 percent of the total) cause page faults. What is the effective memory access time? Consider the following page reference string: 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6. Assuming demand paging with four frames, Show which pages are resident under the LRU, FIFO, and Optimal replacement algorithms by filling out the following tables. How many page faults would occur…
- In a computer with a 32-bit data-bus, how many 4-bit wide memory components are used? the answer to this part is 32/4 = 8 components (2-bit wide) I need the answer to part two, please If the size of each 4-bit memory component is 4 x n cells where n = 1G (i.e., 4 x n uniquely addressable locations—n : row, 4 : 2 column/width), what is the total capacity of the memory system? Show your answer in power of 2. (hint: 1000 ~ 210)Consider a computer with 128 MB of main memory, 64 KB of cache, and 4 bytes per memory block. Find out how to split the address (s-r, r, w) so that it can be used for direct mapping.Find out how to split the address into two parts (s and w) for associative mapping.Find out how to split the address into three parts (s-d, d, and w) for set associative mapping. Assume that each cache set has two lines.A SONET STS-1 SPE is mapped into an STS-1 line. An STS-1 SPE frame consists of 87 columns of 9 bytes, or altogether 783 bytes. There are always 8,000 frames per second. The SPE clock is slower than the line clock by a factor of 5 x 10-7 .On average, we expect to find one pointer adjustment for how many SONET frames?
- Assume that a switching component such as a transistor can switch in zero time. We propose to construct a disk-shaped computer chip with such a component. The only limitation is the time it takes to send electronic signals from one edge of the chip to the other. Make the simplifying assumption that electronic signals can travel at 300,000 kilometers per second. What is the limitation on the diameter of a round chip so that any computation result can by used anywhere on the chip at a clock rate of 1 GHz? What are the diameter restrictions if the whole chip should operate at 1 THz = 1012 Hz? Is such a chip feasible?Write an openMP program that calculates the integration of the following function F(x) = 2 x° - x? +2 x For the interval 0 to 5. Processor will be assigned equal parts of the interval to calculate its integration. Let the user enter the number of trapezoids for each interval. Time your execution for different number of processors (2-8). Report your findings.Consider a demand-paging system with a paging disk that has an average access/transfer time of 50 ms. Addresses are translated through a page table in main memory, with an access time of 500 ns per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added a TLB that reduces access time to one memory reference if the page-table entry is in the TLB. Assume that 80% of the accesses are in the TLB and that, of those remaining, 15% (or 3% of the total) cause page faults. We assume that the TLB access time is 20 ns. What is the effective access time?
- Consider a disk drive specifications. with the following 16 surfaces, 512 tracks/surface, 512 sectors/ track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation?Consider a system that implements demand paging without a TLB. The single-level page table is held in memory, and we assume that there are no free frames. Each memory access requires 100 nanoseconds. It takes 6 additional milliseconds to handle a page fault if the victim page is not “dirty” or 12 additional milliseconds if the victim page is “dirty”. Experiments show that the probability of page faulting is 0.00003 (i.e., 0.003% chance) and that the average memory access time is 400ns. What is the percent chance that a page is dirty at the time it is evicted? Hint: Call the “being dirty” probability d and write a simple equation that gives the average data access time as a function of d. Solve for d (the result should be a number between 0 and 1, which you then convert to a percentage).Suppose the processing load of a computing system consists of 50% disk activity, 25% CPU activity, and 25% other IO activity. Your customers are complaining that the system is slow. After research, you discover that you can upgrade your disks and make them 2 times faster than they currently are. You also discovered you can upgrade your CPU to make it 3 times faster than it currently is. Further, you find a way of boosting the other IO operations by a factor of 5. Assuming you have time to implement only one of these enhancements, which one would you choose if you want to achieve the maximum speedup. Show your work.