2. a. Analyze the following MIPS code and find out what exactly it is doing. Explaining what each MIPS instruction does literally is not enough, you need to explain how it contributes to the overall logic. adddu St1, St2, St3 nor St4, St2, Szero sltu St5, St4, St3 bne St5, Szero, exception1_processing What is the specific exception that is being processed at the label exception1_processing? Indicate with a diagram how a very simplified implementation of the same logic is possible in b. hardware. c. Explain with a flow chart and architecture diagram hardware efficient division algorithm may be performed d. Explain why massively parallel implementation of the division algorithm not possible?

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
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2. a. Analyze the following MIPS code and find out what exactly it is doing. Explaining what each
MIPS instruction does literally is not enough, you need to explain how it contributes to the
overall logic.
adddu $t1, $t2, $t3
nor $t4, $t2, Szero
sltu St5, St4, $t3
bne St5, Szero, exception1_processing
What is the specific exception that is being processed at the label exception1_processing?
Indicate with a diagram how a very simplified implementation of the same logic is possible in
b.
hardware.
c. Explain with a flow chart and architecture diagram hardware efficient division algorithm may be
performed
d. Explain why massively parallel implementation of the division algorithm not possible?
Transcribed Image Text:2. a. Analyze the following MIPS code and find out what exactly it is doing. Explaining what each MIPS instruction does literally is not enough, you need to explain how it contributes to the overall logic. adddu $t1, $t2, $t3 nor $t4, $t2, Szero sltu St5, St4, $t3 bne St5, Szero, exception1_processing What is the specific exception that is being processed at the label exception1_processing? Indicate with a diagram how a very simplified implementation of the same logic is possible in b. hardware. c. Explain with a flow chart and architecture diagram hardware efficient division algorithm may be performed d. Explain why massively parallel implementation of the division algorithm not possible?
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