2. A two-stage amplifier is designed for radio frequency communications. (a) Identify the configurations of stage I (include amplifier topology and bias) and stage II (amplifier topology only). Briefly explain the reason for each design. (b) Assume RG is very large. If Rs is designed as 500 ohm, design Rp to have ID of 1 mA. (c) Assume the RD obtained in (b) is 3.5 kohm, and RE is designed as 400 ohm. Determine Rin1, Rin2, and the small-signal gain of vx/Vin, Vout/Vx, and Vout/Vin. Assume the antenna can be equivalent to a signal source with a 50 ohm internal resistance.

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2. A two-stage amplifier is designed for radio frequency communications.
(a) Identify the configurations of stage I (include amplifier topology and bias) and stage
II (amplifier topology only). Briefly explain the reason for each design.
(b) Assume RG is very large. If Rs is designed as 500 ohm, design RD to have ID of 1
mA.
(c) Assume the RD obtained in (b) is 3.5 kohm, and RE is designed as 400 ohm.
Determine Rinl, Rin2, and the small-signal gain of vx/Vin, Vout/Vx, and Vout/Vin. Assume the
antenna can be equivalent to a signal source with a 50 ohm internal resistance.
(d) If the input DC block capacitor C₁ (Assume C₁ = 0.1 μµF) has to be considered for
the frequency response, find the corresponding zero and pole frequencies of stage I.
Vin
{{
VDD
Rint
RD
Rs
M₁
lo
Stage I
RG
Ibias
Rin2
VDD= 5 V
(W/L)₁= 100
HnCox 200 μA/V²
VTH= 0.5 V.
B= 30, VBE_on=0.8V
Fazit
RE
Stage II
Vout
R₁ = 100 22
Transcribed Image Text:2. A two-stage amplifier is designed for radio frequency communications. (a) Identify the configurations of stage I (include amplifier topology and bias) and stage II (amplifier topology only). Briefly explain the reason for each design. (b) Assume RG is very large. If Rs is designed as 500 ohm, design RD to have ID of 1 mA. (c) Assume the RD obtained in (b) is 3.5 kohm, and RE is designed as 400 ohm. Determine Rinl, Rin2, and the small-signal gain of vx/Vin, Vout/Vx, and Vout/Vin. Assume the antenna can be equivalent to a signal source with a 50 ohm internal resistance. (d) If the input DC block capacitor C₁ (Assume C₁ = 0.1 μµF) has to be considered for the frequency response, find the corresponding zero and pole frequencies of stage I. Vin {{ VDD Rint RD Rs M₁ lo Stage I RG Ibias Rin2 VDD= 5 V (W/L)₁= 100 HnCox 200 μA/V² VTH= 0.5 V. B= 30, VBE_on=0.8V Fazit RE Stage II Vout R₁ = 100 22
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