2 GHz. All channels support up to 3 ranks of DIMMS. A DIMM contains multiple chips with the Ilowing properties. Banks have 16K rows and 256 columns. A DRAM chip has 16 banks and x8 interface with a burst rate of 8. a) How many bits does each column (within a row) store? b) What is the capacity of a single chip? c). What is the capacity of a rank d) What is the maximum DRAM capacity supported by the processor a

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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Assume a processor with 2 DDR DRAM channels of width 64 bit, with each channel operating at
1.2 GHz. All channels support up to 3 ranks of DIMMS. A DIMM contains multiple chips with the
following properties. Banks have 16K rows and 256 columns. A DRAM chip has 16 banks and
an x8 interface with a burst rate of 8.
a) How many bits does each column (within a row) store?
b) What is the capacity of a single chip?
c). What is the capacity of a rank
d) What is the maximum DRAM capacity supported by the processor?P
Transcribed Image Text:Assume a processor with 2 DDR DRAM channels of width 64 bit, with each channel operating at 1.2 GHz. All channels support up to 3 ranks of DIMMS. A DIMM contains multiple chips with the following properties. Banks have 16K rows and 256 columns. A DRAM chip has 16 banks and an x8 interface with a burst rate of 8. a) How many bits does each column (within a row) store? b) What is the capacity of a single chip? c). What is the capacity of a rank d) What is the maximum DRAM capacity supported by the processor?P
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