2 *100u 21 DS9 +V V Gs9 + 0.5 = 0.72 V. 0.004 2*100u 0.5 = -0.72 V. DS10 V GS10 +V, %3D 0.004 (j) We observe the following: W13 = 300 µm and W12 = 100 µm hence their B is the same and = 0.02 A/V². The voltage difference between the gates of M12 and M13 is VGS12 - VGS13 = VGs9 – VGS10 = 0.72 + 0.72 V = 1.44 V. %3D The circuit is well matched so we can expect that the 1.44 V will be evenly distributed between M12 and M13. Also, since we expect vo = VR at quiescence we can say that there is no current in RL and VGS12 = 0.72V and VGS13 = -0.72 V. %3D %3D Because there is no current in RL we can say that Ips12 = -IDS13. The quiescent current in the output stage at quiescence is therefore: Ips = 0.5B(VGs - V² = 0.5*0.02*(0.72-0.5) = 484 µA. %3D Because the output stage is biased so as to be always on the amplifier is operating as a class AB type. %3D (k) The total quiescent current is: Ips14 + Ips15 + Ips3 + Ips7 + Ips11 + Ips12 %3D = 100µ+100µ+200µ+100µ+100µ+484µ = 1084 µA. The quiescent power dissipation is therefore 5*1.084m = 5.4 mW.:

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Publisher:Robert L. Boylestad
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Explain simply what they did below?
Figure I shows a complete op-amp circuit with an output load RL. The design has the
following properties.
VDD = 5 V, VSS = 0 V and VR = 2.5 V.
L for all transistors (NMOS and PMOS) = 1 µm.
For the NMOS B= 0.002 A/V² when W = 10 um.
For the PMOS B= 0.002 A/V² when W = 30 µm.
The NMOS threshold voltage is 0.5 V and the PMOS threshold voltage is -0.5 V.
The bias current in RB = 100 µA.
You may assume that all the transistors are in saturation and that the Early voltage is 20 V.
VDD
M14
M15
에 M3
예 M7
M11
M12
M16
M17
M10
CM
vi1 d M1
M18
M2 v2
M19
M9
RL
MB
M13
RB
MA
M5
MB
VR
VSS
Figure 1. A three-stage op-amp with bias reference and Miller compensation.
Question 1. DC bias calculations.
300 um. What will their respective VGs be at quiescence and
j. W12 = 100 µm and W13
the resulting Ips in each case?
k. What is the quiescent power dissipation of the amplifier?
Transcribed Image Text:Figure I shows a complete op-amp circuit with an output load RL. The design has the following properties. VDD = 5 V, VSS = 0 V and VR = 2.5 V. L for all transistors (NMOS and PMOS) = 1 µm. For the NMOS B= 0.002 A/V² when W = 10 um. For the PMOS B= 0.002 A/V² when W = 30 µm. The NMOS threshold voltage is 0.5 V and the PMOS threshold voltage is -0.5 V. The bias current in RB = 100 µA. You may assume that all the transistors are in saturation and that the Early voltage is 20 V. VDD M14 M15 에 M3 예 M7 M11 M12 M16 M17 M10 CM vi1 d M1 M18 M2 v2 M19 M9 RL MB M13 RB MA M5 MB VR VSS Figure 1. A three-stage op-amp with bias reference and Miller compensation. Question 1. DC bias calculations. 300 um. What will their respective VGs be at quiescence and j. W12 = 100 µm and W13 the resulting Ips in each case? k. What is the quiescent power dissipation of the amplifier?
2*100
21 DS9
V GS9
+V,
+ 0.5 = 0.72 V.
%3D
0.004
21 DS10
2*100u
+V,
-0.5 = -0.72 V.
VGS10 =
0.004
()
We observe the following:
W13 = 300 µm and W12 = 100 µm hence their B is the same and = 0.02 A/V².
The voltage difference between the gates of M12 and M13 is
VGS12- VGS13 = VG89 – VGS10 = 0.72 + 0.72 V = 1.44 V.
The circuit is well matched so we can expect that the 1.44 V will be evenly distributed
between M12 and M13. Also, since we expect vo = VR at quiescence we can say that there is
no current in Rị and VGs12 = 0.72V and VGS13 = -0.72 V.
Because there is no current in RL we can say that IDs12 = -IDS13-
The quiescent current in the output stage at quiescence is therefore:
Ips = 0.5B(VGs - V² = 0.5*0.02*(0.72-0.5) = 484 µA.
Because the output stage is biased so as to be always on the amplifier is operating as a class
АB type.
%3D
(k)
The total quiescent current is:
Ips14 + Ips15 + Ips3 + Ips7 + IpsSii + Ips12
100μ+100μ+200μ+ 1 00μ+ 100μ+484μ = 1084 μΑ.
%3D
The quiescent power dissipation is therefore 5*1.084m = 5.4 mW.
Transcribed Image Text:2*100 21 DS9 V GS9 +V, + 0.5 = 0.72 V. %3D 0.004 21 DS10 2*100u +V, -0.5 = -0.72 V. VGS10 = 0.004 () We observe the following: W13 = 300 µm and W12 = 100 µm hence their B is the same and = 0.02 A/V². The voltage difference between the gates of M12 and M13 is VGS12- VGS13 = VG89 – VGS10 = 0.72 + 0.72 V = 1.44 V. The circuit is well matched so we can expect that the 1.44 V will be evenly distributed between M12 and M13. Also, since we expect vo = VR at quiescence we can say that there is no current in Rị and VGs12 = 0.72V and VGS13 = -0.72 V. Because there is no current in RL we can say that IDs12 = -IDS13- The quiescent current in the output stage at quiescence is therefore: Ips = 0.5B(VGs - V² = 0.5*0.02*(0.72-0.5) = 484 µA. Because the output stage is biased so as to be always on the amplifier is operating as a class АB type. %3D (k) The total quiescent current is: Ips14 + Ips15 + Ips3 + Ips7 + IpsSii + Ips12 100μ+100μ+200μ+ 1 00μ+ 100μ+484μ = 1084 μΑ. %3D The quiescent power dissipation is therefore 5*1.084m = 5.4 mW.
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