1b) Which of the memories in the memory hierarchy is best suited for holding each of the following kinds of data? (i) Data that are being used right now. (ii) Data that are being used by a program that is currently running. (iii)Data that need to be saved even when the computer's power is turned off. (iv) Data that are about to be used, or have just been used.
1b) Which of the memories in the memory hierarchy is best suited for holding each of the following kinds of data? (i) Data that are being used right now. (ii) Data that are being used by a program that is currently running. (iii)Data that need to be saved even when the computer's power is turned off. (iv) Data that are about to be used, or have just been used.
Computer Networking: A Top-Down Approach (7th Edition)
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Chapter1: Computer Networks And The Internet
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![la) Draw a clearly labelled diagram of memory hierarchy indicating:
(i) The correct order of SPEED, from the fastest to the slowest
(ii) The correct order of COST, from the most expensive to the cheapest
(iii) The correct order of SIZE, from the largest to the smallest
(iv) The correct order of VOLATILITY, from the most volatile to the least volatile
1b) Which of the memories in the memory hierarchy is best suited for holding each of the
following kinds of data?
(i) Data that are being used right now.
(ii) Data that are being used by a program that is currently running.
(iii)Data that need to be saved even when the computer's power is turned
off.
(iv) Data that are about to be used, or have just been used.
1c) A computer has a 256 KByte, 4-way set associative, write back data cache with the block
size of 32 Bytes. The processor sends 32-bit addresses to the cache controller. Calculate the
number of bits for the Tag, the set-index, and the word-offset.
How many blocks of data does the main memory have?
[Hint: Memory is Byte Addressable]
1d) The timing for a particular cache is as follows: Checking the cache takes 1 cycle. If there is
a hit, the data is returned to the CPU at the end of the first cycle. If there is a miss, it takes
additional ten (10) cycles to retrieve the word from the main memory, store it in the cache and
return it to the CPU. If we want an average access time of 1.4 cycles, what should be the
minimum possible value of the cache hit ratio?](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F1a03855e-6142-4625-8324-2469a3d09de4%2Ff8d6f736-7e90-48d2-a535-3a00938a027b%2F0altqr5_processed.png&w=3840&q=75)
Transcribed Image Text:la) Draw a clearly labelled diagram of memory hierarchy indicating:
(i) The correct order of SPEED, from the fastest to the slowest
(ii) The correct order of COST, from the most expensive to the cheapest
(iii) The correct order of SIZE, from the largest to the smallest
(iv) The correct order of VOLATILITY, from the most volatile to the least volatile
1b) Which of the memories in the memory hierarchy is best suited for holding each of the
following kinds of data?
(i) Data that are being used right now.
(ii) Data that are being used by a program that is currently running.
(iii)Data that need to be saved even when the computer's power is turned
off.
(iv) Data that are about to be used, or have just been used.
1c) A computer has a 256 KByte, 4-way set associative, write back data cache with the block
size of 32 Bytes. The processor sends 32-bit addresses to the cache controller. Calculate the
number of bits for the Tag, the set-index, and the word-offset.
How many blocks of data does the main memory have?
[Hint: Memory is Byte Addressable]
1d) The timing for a particular cache is as follows: Checking the cache takes 1 cycle. If there is
a hit, the data is returned to the CPU at the end of the first cycle. If there is a miss, it takes
additional ten (10) cycles to retrieve the word from the main memory, store it in the cache and
return it to the CPU. If we want an average access time of 1.4 cycles, what should be the
minimum possible value of the cache hit ratio?
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