13. We wish to design the CE stage of Figure for a voltage gain of 20. What is the minimum allowable supply voltage if Q1 must remain in the active mode? Assume VA=∞and VBE = 0.8V. J Vcc= 2.5 V 50 Κ Ω -o Vout Vinº Ка O 1320mV O 1.32mV O 132mv None of the mentioned. 0.132V
13. We wish to design the CE stage of Figure for a voltage gain of 20. What is the minimum allowable supply voltage if Q1 must remain in the active mode? Assume VA=∞and VBE = 0.8V. J Vcc= 2.5 V 50 Κ Ω -o Vout Vinº Ка O 1320mV O 1.32mV O 132mv None of the mentioned. 0.132V
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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Question
![13. We wish to design the CE stage of
Figure for a voltage gain of 20. What is the
minimum allowable supply voltage if Q1
must remain in the active mode? Assume
VA=∞and VBE = 0.8V.
Vcc=2.5 V
50 Κ Ω
-o Vout
Vinº
O 1320mV
O 1.32mv
O 132mV
O 0.132V
Q₁
None of the mentioned.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F0a8612e4-4e2c-4d69-9715-91c7d9483b4d%2F50a0ccc2-da56-4db5-a805-6482962efe67%2Fjgqpcfu_processed.jpeg&w=3840&q=75)
Transcribed Image Text:13. We wish to design the CE stage of
Figure for a voltage gain of 20. What is the
minimum allowable supply voltage if Q1
must remain in the active mode? Assume
VA=∞and VBE = 0.8V.
Vcc=2.5 V
50 Κ Ω
-o Vout
Vinº
O 1320mV
O 1.32mv
O 132mV
O 0.132V
Q₁
None of the mentioned.
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