11. *11. Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16-byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout the course of running a program. Suppose this computer uses direct-mapped cache. The format of a memory address as seen by the cache is shown here: Tag 4 bits Block 2 bits Offset 2 bits The system accesses memory addresses in this exact order: OX6E, oxB9, ox17, OXE0, ox4E, ox4F, ox50, ox91, oxA8, oxA9, OXAB, OXAD, ox93, and ox94. The memory addresses of the first four accesses have been loaded into the cache blocks as shown below. (The contents of the tag are shown in binary, and the cache "contents" are simply the address stored at that cache location.) Cache contents Tag contents (represented by address) Block 0 1110 OXEO OXE1 OXE2 ОХЕЗ Cache contents Tag contents (represented by address) Block 1 0001 Ox14 Ox15 Ox16 Ox17 Block 2 1011 ОхB8 ОхВ9 OXBA OXBB Block 3 0110 Ox6C Ox6D OX6E OX6F

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What memory blocks will be in the cache after the last address has been accessed?

11. *11. Suppose we have a computer that uses a memory address word
size of 8 bits. This computer has a 16-byte cache with 4 bytes per
block. The computer accesses a number of memory locations
throughout the course of running a program.
Suppose this computer uses direct-mapped cache. The format of a
memory address as seen by the cache is shown here:
Tag
4 bits
Block
2 bits
Offset
2 bits
Transcribed Image Text:11. *11. Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16-byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout the course of running a program. Suppose this computer uses direct-mapped cache. The format of a memory address as seen by the cache is shown here: Tag 4 bits Block 2 bits Offset 2 bits
The system accesses memory addresses in this exact order: OX6E,
oxB9, ox17, OXE0, ox4E, ox4F, ox50, ox91, oxA8, oxA9, OXAB,
OXAD, ox93, and ox94. The memory addresses of the first four
accesses have been loaded into the cache blocks as shown below.
(The contents of the tag are shown in binary, and the cache
"contents" are simply the address stored at that cache location.)
Cache contents
Tag
contents (represented by address)
Block 0
1110
OXEO
OXE1
OXE2
ОХЕЗ
Cache contents
Tag
contents (represented by address)
Block 1
0001
Ox14
Ox15
Ox16
Ox17
Block 2
1011
ОхB8
ОхВ9
OXBA
OXBB
Block 3
0110
Ox6C
Ox6D
OX6E
OX6F
Transcribed Image Text:The system accesses memory addresses in this exact order: OX6E, oxB9, ox17, OXE0, ox4E, ox4F, ox50, ox91, oxA8, oxA9, OXAB, OXAD, ox93, and ox94. The memory addresses of the first four accesses have been loaded into the cache blocks as shown below. (The contents of the tag are shown in binary, and the cache "contents" are simply the address stored at that cache location.) Cache contents Tag contents (represented by address) Block 0 1110 OXEO OXE1 OXE2 ОХЕЗ Cache contents Tag contents (represented by address) Block 1 0001 Ox14 Ox15 Ox16 Ox17 Block 2 1011 ОхB8 ОхВ9 OXBA OXBB Block 3 0110 Ox6C Ox6D OX6E OX6F
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