10- Assume we have a 32KB virtually indexed physically tagged (VIPT) cache. If you know that the cache block size is 64B. If our Operating System (OS) uses 8KB pages, what is the maximum number of sets our cache can have while still be able to use the virtual address to do indexing. Hint: To be able to do indexing using the virtual address, the index bits should be part of the page offset, because page offset will be the same in virtual and physical addresses. A-128 sets B-256 sets A-15 bits - 16MB 11- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4- way associative, virtually-indexed virtually-tagged (VIVT) and has a block size of 16B. How many bits are needed for the tag? C-28 bits B-17 bits C-1024 sets 12- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4- way associative, virtually-indexed virtually-tagged (VIVT) and has a block size of 16B. How many bits are needed for the index? A-4 bits B-11 bits D- 28 bits 13- Choose from the following techniques one that can be used to reduce cold misses: B-1GB - Using larger cache blocks can ncrease hit rate crease number of sets D- 16 sets C-16 bits A- Branch prediction B- Multi-level cache C- Forwarding D- Prefetching 14- Assume a hierarchical page table. If our base page size is 2KB and we use 64-bit addresses, what page size should we support to skip two translation levels? D-4 bits C- 128MB D-512KB B- Save memory bandwidth D- (All answers)
10- Assume we have a 32KB virtually indexed physically tagged (VIPT) cache. If you know that the cache block size is 64B. If our Operating System (OS) uses 8KB pages, what is the maximum number of sets our cache can have while still be able to use the virtual address to do indexing. Hint: To be able to do indexing using the virtual address, the index bits should be part of the page offset, because page offset will be the same in virtual and physical addresses. A-128 sets B-256 sets A-15 bits - 16MB 11- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4- way associative, virtually-indexed virtually-tagged (VIVT) and has a block size of 16B. How many bits are needed for the tag? C-28 bits B-17 bits C-1024 sets 12- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4- way associative, virtually-indexed virtually-tagged (VIVT) and has a block size of 16B. How many bits are needed for the index? A-4 bits B-11 bits D- 28 bits 13- Choose from the following techniques one that can be used to reduce cold misses: B-1GB - Using larger cache blocks can ncrease hit rate crease number of sets D- 16 sets C-16 bits A- Branch prediction B- Multi-level cache C- Forwarding D- Prefetching 14- Assume a hierarchical page table. If our base page size is 2KB and we use 64-bit addresses, what page size should we support to skip two translation levels? D-4 bits C- 128MB D-512KB B- Save memory bandwidth D- (All answers)
Computer Networking: A Top-Down Approach (7th Edition)
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Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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![10- Assume we have a 32KB virtually indexed physically tagged (VIPT)
cache. If you know that the cache block size is 64B. If our Operating System
(OS) uses 8KB pages, what is the maximum number of sets our cache can
have while still be able to use the virtual address to do indexing.
Hint: To be able to do indexing using the virtual address, the index bits should be
part of the page offset, because page offset will be the same in virtual and physical
addresses.
A- 128 sets
- 16MB
B-256 sets
A-15 bits
11- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4-
way associative, virtually-indexed virtually-tagged (VIVT) and has a block
size of 16B. How many bits are needed for the tag?
C-28 bits
B-17 bits
C-1024 sets
B-1GB
12- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4-
way associative, virtually-indexed virtually-tagged (VIVT) and has a block
size of 16B. How many bits are needed for the index?
D-28 bits
B-11 bits
A-4 bits
13- Choose from the following techniques one that can be used to reduce
cold misses:
A-Branch prediction B- Multi-level cache
C- Forwarding D- Prefetching
14- Assume a hierarchical page table. If our base page size is 2KB and we use
64-bit addresses, what page size should we support to skip two translation
levels?
C-16 bits
D-16 sets
C-128MB
--Using larger cache blocks can
Increase hit rate
crease number of sets D- (All answers)
D-4 bits
D-512KB
B- Save memory bandwidth](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F0a997a6f-a222-4716-adb9-ab223c542cab%2F45f0fe02-62a3-44a8-8313-ed434b77a067%2F4lcwxl_processed.jpeg&w=3840&q=75)
Transcribed Image Text:10- Assume we have a 32KB virtually indexed physically tagged (VIPT)
cache. If you know that the cache block size is 64B. If our Operating System
(OS) uses 8KB pages, what is the maximum number of sets our cache can
have while still be able to use the virtual address to do indexing.
Hint: To be able to do indexing using the virtual address, the index bits should be
part of the page offset, because page offset will be the same in virtual and physical
addresses.
A- 128 sets
- 16MB
B-256 sets
A-15 bits
11- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4-
way associative, virtually-indexed virtually-tagged (VIVT) and has a block
size of 16B. How many bits are needed for the tag?
C-28 bits
B-17 bits
C-1024 sets
B-1GB
12- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4-
way associative, virtually-indexed virtually-tagged (VIVT) and has a block
size of 16B. How many bits are needed for the index?
D-28 bits
B-11 bits
A-4 bits
13- Choose from the following techniques one that can be used to reduce
cold misses:
A-Branch prediction B- Multi-level cache
C- Forwarding D- Prefetching
14- Assume a hierarchical page table. If our base page size is 2KB and we use
64-bit addresses, what page size should we support to skip two translation
levels?
C-16 bits
D-16 sets
C-128MB
--Using larger cache blocks can
Increase hit rate
crease number of sets D- (All answers)
D-4 bits
D-512KB
B- Save memory bandwidth
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