Homework Help is Here – Start Your Trial Now!
Engineering
Computer Engineering
10- Assume we have a 32KB virtually indexed physically tagged (VIPT) cache. If you know that the cache block size is 64B. If our Operating System (OS) uses 8KB pages, what is the maximum number of sets our cache can have while still be able to use the virtual address to do indexing. Hint: To be able to do indexing using the virtual address, the index bits should be part of the page offset, because page offset will be the same in virtual and physical addresses. A-128 sets B-256 sets A-15 bits - 16MB 11- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4- way associative, virtually-indexed virtually-tagged (VIVT) and has a block size of 16B. How many bits are needed for the tag? C-28 bits B-17 bits C-1024 sets 12- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4- way associative, virtually-indexed virtually-tagged (VIVT) and has a block size of 16B. How many bits are needed for the index? A-4 bits B-11 bits D- 28 bits 13- Choose from the following techniques one that can be used to reduce cold misses: B-1GB - Using larger cache blocks can ncrease hit rate crease number of sets D- 16 sets C-16 bits A- Branch prediction B- Multi-level cache C- Forwarding D- Prefetching 14- Assume a hierarchical page table. If our base page size is 2KB and we use 64-bit addresses, what page size should we support to skip two translation levels? D-4 bits C- 128MB D-512KB B- Save memory bandwidth D- (All answers)

10- Assume we have a 32KB virtually indexed physically tagged (VIPT) cache. If you know that the cache block size is 64B. If our Operating System (OS) uses 8KB pages, what is the maximum number of sets our cache can have while still be able to use the virtual address to do indexing. Hint: To be able to do indexing using the virtual address, the index bits should be part of the page offset, because page offset will be the same in virtual and physical addresses. A-128 sets B-256 sets A-15 bits - 16MB 11- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4- way associative, virtually-indexed virtually-tagged (VIVT) and has a block size of 16B. How many bits are needed for the tag? C-28 bits B-17 bits C-1024 sets 12- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4- way associative, virtually-indexed virtually-tagged (VIVT) and has a block size of 16B. How many bits are needed for the index? A-4 bits B-11 bits D- 28 bits 13- Choose from the following techniques one that can be used to reduce cold misses: B-1GB - Using larger cache blocks can ncrease hit rate crease number of sets D- 16 sets C-16 bits A- Branch prediction B- Multi-level cache C- Forwarding D- Prefetching 14- Assume a hierarchical page table. If our base page size is 2KB and we use 64-bit addresses, what page size should we support to skip two translation levels? D-4 bits C- 128MB D-512KB B- Save memory bandwidth D- (All answers)

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
See similar textbooks
icon
Related questions
Question
Answers only please
10- Assume we have a 32KB virtually indexed physically tagged (VIPT) cache. If you know that the cache block size is 64B. If our Operating System (OS) uses 8KB pages, what is the maximum number of sets our cache can have while still be able to use the virtual address to do indexing. Hint: To be able to do indexing using the virtual address, the index bits should be part of the page offset, because page offset will be the same in virtual and physical addresses. A- 128 sets - 16MB B-256 sets A-15 bits 11- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4- way associative, virtually-indexed virtually-tagged (VIVT) and has a block size of 16B. How many bits are needed for the tag? C-28 bits B-17 bits C-1024 sets B-1GB 12- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4- way associative, virtually-indexed virtually-tagged (VIVT) and has a block size of 16B. How many bits are needed for the index? D-28 bits B-11 bits A-4 bits 13- Choose from the following techniques one that can be used to reduce cold misses: A-Branch prediction B- Multi-level cache C- Forwarding D- Prefetching 14- Assume a hierarchical page table. If our base page size is 2KB and we use 64-bit addresses, what page size should we support to skip two translation levels? C-16 bits D-16 sets C-128MB --Using larger cache blocks can Increase hit rate crease number of sets D- (All answers) D-4 bits D-512KB B- Save memory bandwidth
Transcribed Image Text:10- Assume we have a 32KB virtually indexed physically tagged (VIPT) cache. If you know that the cache block size is 64B. If our Operating System (OS) uses 8KB pages, what is the maximum number of sets our cache can have while still be able to use the virtual address to do indexing. Hint: To be able to do indexing using the virtual address, the index bits should be part of the page offset, because page offset will be the same in virtual and physical addresses. A- 128 sets - 16MB B-256 sets A-15 bits 11- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4- way associative, virtually-indexed virtually-tagged (VIVT) and has a block size of 16B. How many bits are needed for the tag? C-28 bits B-17 bits C-1024 sets B-1GB 12- Assume we have a 32-bit processor with a 128KB size L1 Cache that is 4- way associative, virtually-indexed virtually-tagged (VIVT) and has a block size of 16B. How many bits are needed for the index? D-28 bits B-11 bits A-4 bits 13- Choose from the following techniques one that can be used to reduce cold misses: A-Branch prediction B- Multi-level cache C- Forwarding D- Prefetching 14- Assume a hierarchical page table. If our base page size is 2KB and we use 64-bit addresses, what page size should we support to skip two translation levels? C-16 bits D-16 sets C-128MB --Using larger cache blocks can Increase hit rate crease number of sets D- (All answers) D-4 bits D-512KB B- Save memory bandwidth
Expert Solution
trending now

Trending now

This is a popular solution!

steps

Step by step

Solved in 7 steps

SEE SOLUTIONCheck out a sample Q&A here
Blurred answer
Recommended textbooks for you
Computer Networking: A Top-Down Approach (7th Edi…
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Concepts of Database Management
Concepts of Database Management
Computer Engineering
ISBN:
9781337093422
Author:
Joy L. Starks, Philip J. Pratt, Mary Z. Last
Publisher:
Cengage Learning
Prelude to Programming
Prelude to Programming
Computer Engineering
ISBN:
9780133750423
Author:
VENIT, Stewart
Publisher:
Pearson Education
Sc Business Data Communications and Networking, T…
Sc Business Data Communications and Networking, T…
Computer Engineering
ISBN:
9781119368830
Author:
FITZGERALD
Publisher:
WILEY
SEE MORE TEXTBOOKS