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1.Write a Verilog code and a test bench to implement a ROM block to save the values specified in table 2, i.e. memory[X]=X^2. $iverilog -o main *.v $vvp main Address = 5 OUT= 25 Address = 6 OUT= 36

1.Write a Verilog code and a test bench to implement a ROM block to save the values specified in table 2, i.e. memory[X]=X^2. $iverilog -o main *.v $vvp main Address = 5 OUT= 25 Address = 6 OUT= 36

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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You have to print screenshot for the 3 codes as described below 1.Write a Verilog code and a test bench to implement a ROM block to save the values specified in table 2, i.e. memory[X]=X^2. $iverilog -o main *.v $vvp main 5 OUT= 25 6 OUT= Address = Address = 36 2.Write a Verilog code and a test bench to implement a ROM block to save the values specified in table 2, i.e. memory[X]=X^3. $vvp main Address = 1 OUT= 1 Address = 2 OUT= 8 Address = 4 OUT= 64 3. Build a new module which takes X as an input while the output Y = 2X^2 + X^3 + X, using the ROM modules you built in parts 1 and 2. $iverilog -o main *.v $vvp main Address = 1 ,2X^2+X^3+X= 4 Address = 2 ,2X^2+X^3+X= 18 able2 X^2 X^3 X^2 X^3 1 9 81 729 2 4 8 10 100 1000 3 9 27 11 121 1331 4 16 64 12 144 1782 5 25 125 13 169 2197 6 36 216 14 196 2744 49 343 15 225 3375 8 64 512|
Transcribed Image Text:You have to print screenshot for the 3 codes as described below 1.Write a Verilog code and a test bench to implement a ROM block to save the values specified in table 2, i.e. memory[X]=X^2. $iverilog -o main *.v $vvp main 5 OUT= 25 6 OUT= Address = Address = 36 2.Write a Verilog code and a test bench to implement a ROM block to save the values specified in table 2, i.e. memory[X]=X^3. $vvp main Address = 1 OUT= 1 Address = 2 OUT= 8 Address = 4 OUT= 64 3. Build a new module which takes X as an input while the output Y = 2X^2 + X^3 + X, using the ROM modules you built in parts 1 and 2. $iverilog -o main *.v $vvp main Address = 1 ,2X^2+X^3+X= 4 Address = 2 ,2X^2+X^3+X= 18 able2 X^2 X^3 X^2 X^3 1 9 81 729 2 4 8 10 100 1000 3 9 27 11 121 1331 4 16 64 12 144 1782 5 25 125 13 169 2197 6 36 216 14 196 2744 49 343 15 225 3375 8 64 512|
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