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1. Write a VHDL description for 32x8 RAM. This RAM has the ports: clk, en,rdwr,address, data_in,data_out. In the positive edge of the clock: if en=1 and rdwr =0 then the data stored in address will be loaded to data_out pins (read operation). If en=1 and rdwr = 1 then the data in the data_in bus will be stored in the specified address (write operation). If en = 0 then nothing will be done in the memory (no read and no write) 2. Write a test bench for this RAM.

1. Write a VHDL description for 32x8 RAM. This RAM has the ports: clk, en,rdwr,address, data_in,data_out. In the positive edge of the clock: if en=1 and rdwr =0 then the data stored in address will be loaded to data_out pins (read operation). If en=1 and rdwr = 1 then the data in the data_in bus will be stored in the specified address (write operation). If en = 0 then nothing will be done in the memory (no read and no write) 2. Write a test bench for this RAM.

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Using VHDL
1. Write a VHDL description for 32x8 RAM. This RAM has the ports: clk, en,rdwr,address, data_in,data_out. In the positive edge of the clock: if en=1 and rdwr = 0 then the data stored in address will be loaded to data_out pins (read operation). If en=1 and rdwr =1 then the data in the data_in bus will be stored in the specified address (write operation). If en = 0 then nothing will be done in the memory (no read and no write) 2. Write a test bench for this RAM.
Transcribed Image Text:1. Write a VHDL description for 32x8 RAM. This RAM has the ports: clk, en,rdwr,address, data_in,data_out. In the positive edge of the clock: if en=1 and rdwr = 0 then the data stored in address will be loaded to data_out pins (read operation). If en=1 and rdwr =1 then the data in the data_in bus will be stored in the specified address (write operation). If en = 0 then nothing will be done in the memory (no read and no write) 2. Write a test bench for this RAM.
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