**Title: Designing a 3-to-8 Decoder Using Verilog****Objective:** Write a Verilog program for a 3-to-8 decoder using the provided Truth Table 1. Please note that you are not allowed to use a 2-to-4 decoder to build your 3-to-8 decoder.**Truth Table 1 Details:**The truth table defines the logic for a 3-to-8 decoder. Here is a detailed explanation of the table:- **Inputs:** - **En:** Enable (1 bit) - **A2, A1, A0:** Address lines (3 bits)- **Outputs:** - **z0 to z7:** Output lines (8 bits)The table provides the output states for all combinations of the input lines when the enable (En) line is activated (1). If En is 0, all outputs (z0 to z7) are 0, regardless of the address lines.- If `En` is 0, outputs `z0` to `z7` are all 0.- If `En` is 1: - `A2 A1 A0 = 000`, then `z0` is 1; others are 0. - `A2 A1 A0 = 001`, then `z1` is 1; others are 0. - `A2 A1 A0 = 010`, then `z2` is 1; others are 0. - `A2 A1 A0 = 011`, then `z3` is 1; others are 0. - `A2 A1 A0 = 100`, then `z4` is 1; others are 0. - `A2 A1 A0 = 101`, then `z5` is 1; others are 0. - `A2 A1 A0 = 110`, then `z6` is 1; others are 0. - `A2 A1 A0 = 111`, then `z7` is 1; others are 0.Each row of the table represents a condition where only one of the outputs is high (1) when the enable is active, essentially decoding the 3-bit input into one of the 8 outputs.

For the given truth table to 3 to 8 decoder we have to write the verilog codemodule deocder_3x8(a,en,z); input [2:0]a; input en; output reg [7:0]z; always@(*) begin if (en==1) case(a) 3'b000:z=8'b00000011; 3'b001:z=8'b00000110; 3'b010:z=8'b00001100; 3'b011:z=8'b00011000; 3'b100:z=8'b00110000; 3'b101:z=8'b01100000; 3'b110:z=8'b11000000; 3'b111:z=8'b10000000; endcase else z=8'bx; end endmodule