1. What is the size of the main memory of this system? 2. What is the size of the cache memory of this system? 3. If the CPU requests to read memory address A1 25 BA, what data does the CPU receive? 4. If the CPU requests to read memory address A1 35 C2, what data does the CPU receive? 5. If we access memory in the following order in cache system A: A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 how many cache misses would occur for the data request?

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
icon
Related questions
Question
Just need answer
The system is byte-addressable and the block size is one word (4 bytes). The tag and line number
are represented with a binary numbers. The contents of words in the block are represented with
hexadecimal.
Tag
Line
Number
10
1000 0110
0100 1101
1001
10
1000 0110
0100 1110
1001
10
1000 0110
0100 1111
1001
10
1000 0111
0100 0000
1101
Word within block
00 01 10 11
20166116 C116 2116
32167216C216D216
421682164116 A216
E21692165216 B216
Transcribed Image Text:The system is byte-addressable and the block size is one word (4 bytes). The tag and line number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag Line Number 10 1000 0110 0100 1101 1001 10 1000 0110 0100 1110 1001 10 1000 0110 0100 1111 1001 10 1000 0111 0100 0000 1101 Word within block 00 01 10 11 20166116 C116 2116 32167216C216D216 421682164116 A216 E21692165216 B216
1. What is the size of the main memory of this system?
2. What is the size of the cache memory of this system?
3. If the CPU requests to read memory address A1 25 BA, what data does the CPU receive?
4. If the CPU requests to read memory address A1 35 C2, what data does the CPU receive?
5. If we access memory in the following order in cache system A:
A1 FF B8
B1 FF B8
A1 FF B8
B1 FF B8
A1 FF B8
B1 FF B8
how many cache misses would occur for the data request?
Transcribed Image Text:1. What is the size of the main memory of this system? 2. What is the size of the cache memory of this system? 3. If the CPU requests to read memory address A1 25 BA, what data does the CPU receive? 4. If the CPU requests to read memory address A1 35 C2, what data does the CPU receive? 5. If we access memory in the following order in cache system A: A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 how many cache misses would occur for the data request?
Expert Solution
steps

Step by step

Solved in 4 steps

Blurred answer
Knowledge Booster
Fundamentals of Input and Output Performance
Learn more about
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.
Similar questions
  • SEE MORE QUESTIONS
Recommended textbooks for you
Database System Concepts
Database System Concepts
Computer Science
ISBN:
9780078022159
Author:
Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:
McGraw-Hill Education
Starting Out with Python (4th Edition)
Starting Out with Python (4th Edition)
Computer Science
ISBN:
9780134444321
Author:
Tony Gaddis
Publisher:
PEARSON
Digital Fundamentals (11th Edition)
Digital Fundamentals (11th Edition)
Computer Science
ISBN:
9780132737968
Author:
Thomas L. Floyd
Publisher:
PEARSON
C How to Program (8th Edition)
C How to Program (8th Edition)
Computer Science
ISBN:
9780133976892
Author:
Paul J. Deitel, Harvey Deitel
Publisher:
PEARSON
Database Systems: Design, Implementation, & Manag…
Database Systems: Design, Implementation, & Manag…
Computer Science
ISBN:
9781337627900
Author:
Carlos Coronel, Steven Morris
Publisher:
Cengage Learning
Programmable Logic Controllers
Programmable Logic Controllers
Computer Science
ISBN:
9780073373843
Author:
Frank D. Petruzella
Publisher:
McGraw-Hill Education