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1. What is the optimum size of the memory?

1. What is the optimum size of the memory?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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1. What is the optimum size of the memory?
2. What is the size of the state decoder?

   

2 x 4
   

3 x 8
   

4 x 16
   

5 x 32
   

6 x 64

3. Which of the following is the correct input to the state counter?

   

"0, IR[2:0]"
   

"1, IR[2:0]"
   

"IR[2:0], 0"
   

"IR[2], 0, IR[1:0]"

4. What state/s should activate the CLR control line of the state counter?

ACLOAD PCLOAD + PCINC PCBUS T AC MPU 8. PC ACINÇ READ ALUSEL1 ADD/ SUB/ 8 ALUSELO ! ALUBUS AND / OR RD 8. 8-bit Memory BUS -DRLOAD _B 8 DR -DRBUS 5 AR Control Signals MEMBUS ARLOAD Control 3 IR 3 Unit IRLOAD ALU OPERATIONS SELECT LINES / CONTROL SIGNALS ALU OPERATION ALUSEL1 ALUSELO XOR SUB 1 ADD 1 1 INSTRUCTION SET ARCHITECTURE Each instruction code is composed of eight bits. Bits 7-5 are used for the opcodes, while bits 4-0 are for the address. Instruction Орсode Instruction Format Instruction Орсode Instruction Format XOR 010 010 AAAAA JMP 101 101 AAAAA SUB 011 011AAAAA LDA 110 110 AAAAA ADD 100 100 AAAAA INC 111 111 XXXXX FETCH AND EXECUTE CYCLES (RTL) FETCH CYCLE ADD EXECUTE CYCLE XOR EXECUTE CYCLE FETCH1 AR E PC ADD1 DR E MEM XOR1 DR E MEM FETCH2 DR E MEM, ADD2 АC€ AC + DR XOR2 AC E AC O DR IR E DR[7:5], SUB EXECUTE CYCLE FETCH3 INC EXECUTE CYCLE AR E DR[4:0], SUB1 DR E MEM INC1 AC E AC + 1 PC E PC + 1 SUB2 AC E AC - DR LDA EXECUTE CYCLE JMP EXECUTE CYCLE LDA1 DR E MEM JMP1 PC E DR[4:0] LDA2 AC + DR
Transcribed Image Text:ACLOAD PCLOAD + PCINC PCBUS T AC MPU 8. PC ACINÇ READ ALUSEL1 ADD/ SUB/ 8 ALUSELO ! ALUBUS AND / OR RD 8. 8-bit Memory BUS -DRLOAD _B 8 DR -DRBUS 5 AR Control Signals MEMBUS ARLOAD Control 3 IR 3 Unit IRLOAD ALU OPERATIONS SELECT LINES / CONTROL SIGNALS ALU OPERATION ALUSEL1 ALUSELO XOR SUB 1 ADD 1 1 INSTRUCTION SET ARCHITECTURE Each instruction code is composed of eight bits. Bits 7-5 are used for the opcodes, while bits 4-0 are for the address. Instruction Орсode Instruction Format Instruction Орсode Instruction Format XOR 010 010 AAAAA JMP 101 101 AAAAA SUB 011 011AAAAA LDA 110 110 AAAAA ADD 100 100 AAAAA INC 111 111 XXXXX FETCH AND EXECUTE CYCLES (RTL) FETCH CYCLE ADD EXECUTE CYCLE XOR EXECUTE CYCLE FETCH1 AR E PC ADD1 DR E MEM XOR1 DR E MEM FETCH2 DR E MEM, ADD2 АC€ AC + DR XOR2 AC E AC O DR IR E DR[7:5], SUB EXECUTE CYCLE FETCH3 INC EXECUTE CYCLE AR E DR[4:0], SUB1 DR E MEM INC1 AC E AC + 1 PC E PC + 1 SUB2 AC E AC - DR LDA EXECUTE CYCLE JMP EXECUTE CYCLE LDA1 DR E MEM JMP1 PC E DR[4:0] LDA2 AC + DR
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