1. Prelab: Construct the following truth table to be like the previously mentioned one using two 8x1 multiplexers. A B с X Y S2 S1 So 0 0 0 0 1 1 1 101 100 0 1 0 0 1 O 0 0 1 0 1 0 1 1 0 0 0 1 1 0 1 0 1 H 1 1 0 1 O 0 1 1 1 0 0 Construct the provided circuit and validate all states in the truth table mentioned in the prelab. Ensure that the inputs of the two multiplexers (X and Y) in the [Logisim]are arranged in the same order as the outputs in the truth table (GND for 0 and VCC for 1). MUX. Enable Selectors (S2, S1, SO) 000 MUX Enable

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