Controller Design for a Given Plant Goal We aim to design a controller K(s) to meet the following requirements: ⚫ % Overshoot in the step response y(t) should be less than 5%. ⚫ Settling time of the step response y(t) should be less than 6 seconds. For a unit ramp reference input, the steady-state error should be less than 0.12. 1. PID Controller Design and Validation Question: Consider a plant G(s) = (8+3) (8+2)· Design a PID controller K(s) for it with the following specifications: • • • The % overshoot in the step response y(t) must be less than 4%. The settling time (2% criterion) must be less than 5 seconds. For a unit step disturbance added at the plant input, the steady-state error must be zero. Write down the complete steps you followed using SISO Tool in a numbered list. Your answer should include: a. Error calculations and verification of % overshoot and settling time. b. Snapshots of the root locus and design adjustments leading to the final controller. c. Expression of the final controller K(s) (specify K, Ki, and Ką). d. Step response plot with overshoot and settling time clearly marked with cursors. e. Disturbance rejection plot showing zero steady-state error, with important data points annotated. Note: Ensure your design systematically addresses all performance specifications. Mention the control strategy (e.g., lead compensation, proportional-integral action) you used and justify your choices based on your observations from SISO Tool plots.
Controller Design for a Given Plant Goal We aim to design a controller K(s) to meet the following requirements: ⚫ % Overshoot in the step response y(t) should be less than 5%. ⚫ Settling time of the step response y(t) should be less than 6 seconds. For a unit ramp reference input, the steady-state error should be less than 0.12. 1. PID Controller Design and Validation Question: Consider a plant G(s) = (8+3) (8+2)· Design a PID controller K(s) for it with the following specifications: • • • The % overshoot in the step response y(t) must be less than 4%. The settling time (2% criterion) must be less than 5 seconds. For a unit step disturbance added at the plant input, the steady-state error must be zero. Write down the complete steps you followed using SISO Tool in a numbered list. Your answer should include: a. Error calculations and verification of % overshoot and settling time. b. Snapshots of the root locus and design adjustments leading to the final controller. c. Expression of the final controller K(s) (specify K, Ki, and Ką). d. Step response plot with overshoot and settling time clearly marked with cursors. e. Disturbance rejection plot showing zero steady-state error, with important data points annotated. Note: Ensure your design systematically addresses all performance specifications. Mention the control strategy (e.g., lead compensation, proportional-integral action) you used and justify your choices based on your observations from SISO Tool plots.
Advanced Engineering Mathematics
10th Edition
ISBN:9780470458365
Author:Erwin Kreyszig
Publisher:Erwin Kreyszig
Chapter2: Second-order Linear Odes
Section: Chapter Questions
Problem 1RQ
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Transcribed Image Text:Controller Design for a Given Plant
Goal
We aim to design a controller K(s) to meet the following requirements:
⚫ % Overshoot in the step response y(t) should be less than 5%.
⚫ Settling time of the step response y(t) should be less than 6 seconds.
For a unit ramp reference input, the steady-state error should be less than
0.12.
Transcribed Image Text:1. PID Controller Design and Validation
Question:
Consider a plant G(s) = (8+3) (8+2)·
Design a PID controller K(s) for it with the following specifications:
•
•
•
The % overshoot in the step response y(t) must be less than 4%.
The settling time (2% criterion) must be less than 5 seconds.
For a unit step disturbance added at the plant input, the steady-state error must be zero.
Write down the complete steps you followed using SISO Tool in a numbered list. Your answer should
include:
a. Error calculations and verification of % overshoot and settling time.
b. Snapshots of the root locus and design adjustments leading to the final controller.
c. Expression of the final controller K(s) (specify K, Ki, and Ką).
d. Step response plot with overshoot and settling time clearly marked with cursors.
e. Disturbance rejection plot showing zero steady-state error, with important data points annotated.
Note:
Ensure your design systematically addresses all performance specifications. Mention the control strategy
(e.g., lead compensation, proportional-integral action) you used and justify your choices based on your
observations from SISO Tool plots.
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