1. Given the hit ratio of level-1 cache is 0.1 and the access time is 1, the hit ratio of level-2 cache is 0.2 and the access time is 10, the hit ratio of level-3 cache is 0.3 and the access time is 100, and the hit ratio of the main memory is 0.4 and the access time of the main memory is 1000, what are the CETA, NETA if 3-level cache is applied and the ETA if no cache is applied?

1. Given the hit ratio of level-1 cache is 0.1 and the access time is 1, the hit ratio of level-2 cache is 0.2 and the access time is 10, the hit ratio of level-3 cache is 0.3 and the access time is 100, and the hit ratio of the main memory is 0.4 and the access time of the main memory is 1000, what are the CETA, NETA if 3-level cache is applied and the ETA if no cache is applied?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

A certain two-way set-associative cache has an access time of 4 ns, compared to a miss time of 60 ns. Without the cache, main memory access time was 50 ns. Running a set of bench-marks with and without the cache indicated a speedup of 90%. What is the approximate hit ratio?
On the Motorola 68020 microprocessor, a cache access takes two clock cycles. Data access from main memory over the bus to the processor takes three clock cycles in the case of no wait state insertion; the data are delivered to the processor in parallel with delivery to the cache. a. Calculate the effective length of a memory cycle given a hit ratio of 0.9 and a clocking rate of 16.67 MHz. b. Repeat the calculations assuming insertion of two wait states of one cycle each per memory cycle. What conclusion can you draw from the results?
Cache Performance Please answer the following questions regarding average memory access time (AMAT). a. If a specific cache design has 2% miss rate for a set of benchmarks with a hit latency of 20 cycles and a miss penalty of 200 cycles. What is the AMAT for this cache? b. If another cache design has 5% miss rate for the same set of benchmarks with a hit latency of 13 cycles and a miss penalty of 200 cycles. What is the AMAT for this cache? c. Which cache design is better?
For an 8-word wide cache with the following access times: L1: 10 bus cycles, L2: 500 bus cycles, calculate the effective bandwidth
It would be very helpful if you could give an example of a proper implementation of one of the cache protocols.
i need the answer quickly
Help please
i need the answer quickly
Give the correct solution only
Answer part d only
The hit rate of the memory closest to the ALU is increased from 75% to 80% in a practical cache memory hierarchy. The hit latency (or hit time) for the closest memory is 20ps, while the miss latency is 20ns. What would the expected reduction in the average memory access latency be?