1. Given the following circuit: 5 ns D A F 1ons The gate delays are as shown above the gates. A, B, Care three input, and all of them are varying, as given below: A = 0 at time 0, and stays constant until time = 20 ns, when it changes to 1 and stays constant there after B = 1 at time = 0, and stays at 1 value until time = 35 ns, and then changes to 0 at35 ns, and stays constant after that. C= 0 at time 0 and changes to 1 at 50ns Plot A, B, C upto time = 70 ns. LL

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timing diagram

1. Given the following circuit:
5 ns
D
B
C
1ons
The gate delays are as shown above the gates. A, B, C are three input, and all of them are varying, as
given below:
A = 0 at time 0, and stays constant until time = 20 ns, when it changes to 1 and stays constant there after
B = 1 at time = 0, and stays at 1 value until time = 35 ns, and then changes to 0 at35 ns, and stays
constant after that.
C= 0 at time 0 and changes to 1 at 50ns
Plot A, B, C upto time = 70 ns.
LL
Transcribed Image Text:1. Given the following circuit: 5 ns D B C 1ons The gate delays are as shown above the gates. A, B, C are three input, and all of them are varying, as given below: A = 0 at time 0, and stays constant until time = 20 ns, when it changes to 1 and stays constant there after B = 1 at time = 0, and stays at 1 value until time = 35 ns, and then changes to 0 at35 ns, and stays constant after that. C= 0 at time 0 and changes to 1 at 50ns Plot A, B, C upto time = 70 ns. LL
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