1. Design a simple logic circuit for a Set/Reset (SR) Latch, based on any actual application of latches. 2.) Describe your design using at least three (4) sentences.    Note: Look at the example guide on the image.

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1. Design a simple logic circuit for a Set/Reset (SR) Latch, based on any actual application of latches.

2.) Describe your design using at least three (4) sentences. 

 

Note: Look at the example guide on the image.

 

Clocked SR Latch
The figure shows a NOR-based SR latch with a clock added. The latch is
responsive to inputs S and Ronly when CLKis high.
R
E-
When CLK is low, the latch retains its current state. Observe that Q changes state -
• When S goes high during positive CLK
• On leading CLK edge after changes in S&R during CLK low time.
A positive glitch in S while CLK is high
When R goes high during positive CLK
Transcribed Image Text:Clocked SR Latch The figure shows a NOR-based SR latch with a clock added. The latch is responsive to inputs S and Ronly when CLKis high. R E- When CLK is low, the latch retains its current state. Observe that Q changes state - • When S goes high during positive CLK • On leading CLK edge after changes in S&R during CLK low time. A positive glitch in S while CLK is high When R goes high during positive CLK
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