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1. Design a sequence detector circuit in verilog. The circuit is supposed to have a one-bit digital input. When you provide the last two digits of your student ID to the input (starting from least significant) the output of the circuit will go high. 2. Draw the state diagram. 3. Write the verilog code.

1. Design a sequence detector circuit in verilog. The circuit is supposed to have a one-bit digital input. When you provide the last two digits of your student ID to the input (starting from least significant) the output of the circuit will go high. 2. Draw the state diagram. 3. Write the verilog code.

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
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Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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1. Design a sequence detector circuit in verilog. The circuit is supposed to have a one-bit digital input. When you provide the last two digits of your student ID to the input (starting from least significant) the output of the circuit will go high. 2. Draw the state diagram. 3. Write the verilog code. 4. a. Draw the circuit block diagram showing the state memory and next state and output logic blocks (similar to the figure provided below). b. Inside each block write the corresponding verilog code. c. Mark the verilog signal name on each bus arrow.
Transcribed Image Text:1. Design a sequence detector circuit in verilog. The circuit is supposed to have a one-bit digital input. When you provide the last two digits of your student ID to the input (starting from least significant) the output of the circuit will go high. 2. Draw the state diagram. 3. Write the verilog code. 4. a. Draw the circuit block diagram showing the state memory and next state and output logic blocks (similar to the figure provided below). b. Inside each block write the corresponding verilog code. c. Mark the verilog signal name on each bus arrow.
inputs : Next-state excitation Logic Output Logic State current state Memory outputs F G clock input clock signal
Transcribed Image Text:inputs : Next-state excitation Logic Output Logic State current state Memory outputs F G clock input clock signal
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